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general description the MAX3956 is an 11.3gbps, highly-integrated, low- power transceiver with digital diagnostics monitoring (ddm) designed for next-generation ethernet transmis - sion systems. the receiver incorporates a limiting ampli - fier and loss-of-signal (los) circuit. the limiting ampli - fier features dual-path architecture optimizing the perfor - mance for signals up to 4.25gbps and up to 11.3gbps, respectively. the transmitter incorporates maxims propri - etary dc-coupled laser driver interface and closed-loop control of laser average power. this part is optimized to enable 0.8w maximum power dissipation target of sfp+ msa based modules. the MAX3956 supports differential ac-coupled signaling with 50 termination at rx input, rx output, and tx input. the tx output is a dc-coupled 25 laser diode interface with dedicated pins for the laser anode (touta) and the laser cathode (toutc). an integrated 12-bit analog-to-digital converter (adc) is utilized to provide digital monitors of internal/external temperature, v cc , and received signal strength indica - tion (rssi). the MAX3956s digital monitors and the use of a 2-wire or 3-wire slave interface enables configuration through a digital-only microcontroller (c). the MAX3956 operates from a single +3.3v supply and over a -40c to +95c temperature range and is available in a standard 5mm x 5mm, 32-pin tqfn-ep package. applications 10gbase-lr sfp+ optical transceivers benefts and features low power consumption enables < 0.8w total sfp+ module power dissipation 380mw typical ic power dissipation at 3.3v (i ld_mod = 45ma, i bias = 45ma) flexibility multirate up to 11.3gbps (nrz) operation with rate select for 1.25gbps to 4.25gbps operation programmable laser-diode modulation current from 10ma to 85ma programmable tx input equalization and rx output deemphasis safety and monitoring integrated eye safety features with maskable fault and interrupt signal generation analog monitors with integrated 12-bit adc, fully supporting sff-8472 ddm accurate analog measurements high-accuracy temperature, v cc , and rssi sensors enables us e of simple digital-only c ordering information appears at end of data sheet. simplifed block diagram lpf mux 4 g 10 g rx - los 50 50 50 50 2 - wire / 3 - wire csel sda scl rin + rin - los rout + rout - 50 50 tin + tin - equalizer dc - coupled laser driver apc tx - los v ccto vout toutc touta ddm vcc temp rssi tx - power badc 1 . 25 gbps to 11 . 3 gbps , dual - path limiting amplifier 1 . 25 gbps to 11 . 3 gbps , dc - coupled laser driver rssi 19-6787; rev 3; 9/14 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface
voltage at v ccx , v ccro , v cct , v ccto ............... -0.3v to 4.0v voltage at regfilt .............................................. -0.3v to 2.0v current into v ccto ....................................... -15ma to +180ma current into regfilt ...................................... -15ma to +15ma current into touta and toutc .................................. +150ma current into vout ............................................. -2ma to +90ma current into tin+, tin-, rin+, and rin- ......... -15ma to +15ma current into rout+ and rout- ..................... -30ma to +30ma voltage at tin+, tin-, rin+, rin-, los, disable, fault, mdin, rssi, scl, sda, intrpt, and csel -0.3v to (v ccx + 0.3v) voltage at tsns, tgnd ....................................... -0.3v to 1.2v voltage at badc, i.c. ............................................... -0.3v to 2v voltage at touta ................ (v ccto - 1.3v) to (v ccto + 1.3v) voltage at toutc and vout ............... 0.3v to (v ccto - 0.4v) continuous power dissipation (t a = +70c) tqfn (derate 34.5mw/ c above +70 c) .................. 2759mw junction temperature ...................................................... +150 c storage temperature range ............................ -55 c to +150 c lead temperature (soldering, 10s) ................................. +300 c soldering temperature (reflow) ....................................... +260 c tqfn junction-to-ambient thermal resistance ( ja ) .......... 29c/w junction-to-case thermal resistance ( jc ) .............. 1.7c/w (note 1) (v ccx = v ccro = v cct = 2.85v to 3.47v, v ccto = 2.97v to 3.47v, v gnd = 0v, t a = -40 c to +95 c. typical values are at v ccx = v ccro = v cct = v ccto = 3.3v, 14 single-ended load for toutc/touta, and t a = +25 c, unless otherwise noted. see figure 1 for electrical setup.) (note 2) parameter symbol conditions min typ max units power-supply current i cc excludes current through toutc and touta; i ld_mod = 60ma, i ld_dc = 40ma, and set_cml[4:0] = 3d 105 130 ma power-on-reset (enable part) v por_de 2.5 v power-on-reset (disable part) v por_as 2.4 v rx input specification input sensitivity for ber < 10 -12 v rin_min 2 31 -1 prbs at 11.3gbps 3 mv p-p differential input resistance r rin 100 rx output specification (set_rxde[2:0] = 0xx) differential output voltage programming range v rout see table 7 for more information 450 800 mv p-p differential output voltage when squelched v rout sq_en = 1 5 mv p-p differential output resistance r rout 100 note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics electrical characteristics maxim integrated 2 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
(v ccx = v ccro = v cct = 2.85v to 3.47v, v ccto = 2.97v to 3.47v, v gnd = 0v, t a = -40 c to +95 c. typical values are at v ccx = v ccro = v cct = v ccto = 3.3v, 14 single-ended load for toutc/touta, and t a = +25 c, unless otherwise noted. see figure 1 for electrical setup.) (note 2) parameter symbol conditions min typ max units deterministic jitter dj 10.3gbps (notes 3, 4, and 5) 4.6 10 ps p-p 11.3gbps (notes 3, 4, and 5) 5.6 11 random jitter rj v rin = 60mv p-p at 10.3gbps, 11111 00000 pattern, set_cml[4:0] = 10d (note 3) 0.25 0.4 ps rms rout rise/fall time t r /t f 20% to 80%, rsel = high, (notes 3 and 5) 11111 00000 pattern 27 35 ps rx oma based loss-of-signal (los) specification (notes 3 and 7) assert/deassert time (note 6) 2.3 80 s los low level setting set_los[6:0] = 8d assert level 6 10 16 mv p-p deassert level 12 16.7 23 los medium level setting set_los[6:0] = 38d assert level 48 mv p-p deassert level 78 los high level setting set_los[6:0] = 101d assert level 121 mv p-p deassert level 197 los output masking time range los_masktime = 0d 0 ms los_masktime = 127d 4.6 los output masking time setting resolution (note 8) 36 s tx input specification differential input resistance r tin 100 laser dc current generator (note 9) maximum dc-on current i dc_max current into vout pin 57 ma minimum dc-on current i dc_min current into vout pin 0.7 1 ma maximum dc-off current i dc_off laser current into vout pin when tx output disabled 0.1 ma laser modulator output (tx_eq[1:0] = 00) (note 10) maximum modulation on- current i ld_mod_max current into toutc, external 10 differential load 85 ma minimum modulation on- current i ld_mod_min current into toutc, external 10 differential load 10 ma modulation output termination r tout single-ended resistance 25 maximum modulation off- current i ld_mod_off current into toutc pin when tx output disabled 0.1 ma modulation current dac stability 10ma < i ld_mod < 85ma (notes 3 and 11) 1.5 4 % electrical characteristics (continued) maxim integrated 3 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
(v ccx = v ccro = v cct = 2.85v to 3.47v, v ccto = 2.97v to 3.47v, v gnd = 0v, t a = -40 c to +95 c. typical values are at v ccx = v ccro = v cct = v ccto = 3.3v, 14 single-ended load for toutc/touta, and t a = +25 c, unless otherwise noted. see figure 1 for electrical setup.) (note 2) parameter symbol conditions min typ max units laser modulator output (tx_eq[1:0] = 00, 10ma < i ld_mod < 85ma, v tin = 150 to 1000mv p-p differential amplitude) (notes 3 and 4) modulation current rise/fall time t r /t f 20% to 80%, 11111 00000 pattern 24 35 ps deterministic jitter dj 10.3gbps 5 11 ps p-p 11.3gbps 5 11 random jitter rj 11111 00000 pattern 0.23 0.55 ps rms apc loop operation specification md average current range i mdin_avg average current sunk from mdin pin 50 2000 a initialization time t_init i dc = 40ma, i mod = 60ma, i dc_init = 0ma, er = 9db, time from restart to i dc and i mod at 90% of steady state 0.1 ms timing requirements (note 3) disable assert time t_off time from rising edge of disable input signal to 10% of i dc and i mod 1.5 10 s disable negate time t_on time from falling edge of disable to i dc and i ld_mod at 90% of steady state when fault = low before reset 8 s fault reset time t_recovery time from negation of latched fault using disable to i ld_mod + i dc at 90% of steady state 8 s fault assert time t_fault time from fault to tx_fault = high, c fault 20pf, r fault = 4.7k 1 3 s disable to reset time time disable must be held high to reset fault 4 s safety features fault assert threshold at vout fault always occurs for vout < v ccto - 2.8v v ccto - 2.8v v fault deassert threshold at vout fault never occurs for vout v ccto - 2.0v v ccto - 2.0v v fault assert threshold at toutc fault always occurs for v toutc < 0.24v 0.24 v fault deassert threshold at toutc fault never occurs for v toutc 0.58v 0.58 v fault threshold at touta fault always occurs for v touta < v ccto - 1.85v v ccto - 1.85v v electrical characteristics (continued) maxim integrated 4 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
(v ccx = v ccro = v cct = 2.85v to 3.47v, v ccto = 2.97v to 3.47v, v gnd = 0v, t a = -40 c to +95 c. typical values are at v ccx = v ccro = v cct = v ccto = 3.3v, 14 single-ended load for toutc/touta, and t a = +25 c, unless otherwise noted. see figure 1 for electrical setup.) (note 2) parameter symbol conditions min typ max units fault deassert threshold at touta fault never occurs for v touta v ccto - 1.34v v ccto - 1.34v v rssi monitor adc resolution 16 bits lsb size 35.5 na rssi input current range 1 2000 a rssi offset current 50 na rssi offset current stability (notes 3 and 12) -120 +150 na rssi gain error (note 3) -4 +4 % tx power monitor tx power monitor accuracy average current into mdin pin 50a < i mdin_avg < 2ma, excluding tracking error (note 3) -25 +25 % badc monitor gain error -2 +2 % adc full scale 1.164 v adc resolution 12 bits adc lsb size 284 v supply voltage monitor (v ccx , v ccro , and v cct ) supply voltage monitor accuracy v ccx = v ccro = v cct > v por_de -2 +2 % adc resolution 12 bits adc lsb size 1.137 mv temperature sensor external temperature sensor accuracy measured with a single pnp device (note 3) -2 +2 c digital inputs (sda, scl, csel, disable, rsel) minimum input voltage high v ih 1.6 v maximum input voltage high v ih v cc v minimum input voltage low v il 0 v electrical characteristics (continued) maxim integrated 5 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
(v ccx = v ccro = v cct = 2.85v to 3.47v, v ccto = 2.97v to 3.47v, v gnd = 0v, t a = -40 c to +95 c. typical values are at v ccx = v ccro = v cct = v ccto = 3.3v, 14 single-ended load for toutc/touta, and t a = +25 c, unless otherwise noted. see figure 1 for electrical setup.) (note 2) parameter symbol conditions min typ max units maximum input voltage low v il 0.8 v input hysteresis v hys 80 mv input leakage current high (sda, disable) i ih input connected to v ccro -10 +10 a input leakage current high (scl, csel, rsel) i ih input connected to v ccro , internal 75k pulldown 20 44 100 a input leakage current low (scl, csel, rsel) i il input connected to gnd -10 +10 a input leakage current low (sda) i il input connected to gnd, internal 75k pullup 20 44 100 a input leakage current low (disable) i il input connected to gnd, internal 7.5k pullup 200 450 800 a digital open-drain output (sda, los, and fault) (note 14) output low voltage v ol external pullup is between 4.7k and 10k to v ccro 0.4 v output high voltage v oh external pullup is between 4.7k and 10k to v ccro v ccro - 0.4 v ccro v digital cmos output (intrpt, los, and fault) (note 14) output low voltage v ol i ol = 1ma 0.4 v output high voltage v oh i oh = 1ma v ccro - 0.4 v 3-wire timing specifications (figure 3) maximum scl clock frequency f scl 1000 khz minimum scl pulse width high t ch 500 ns minimum scl pulse width low t cl 500 ns sda setup time t ds 100 ns sda hold time t dh 100 ns scl rise to sda propagation time t d 12 ns minimum csel pulse width low t csw 500 ns csel leading time before the first scl edge t l 500 ns csel trailing time after the last scl edge t t 500 ns electrical characteristics (continued) maxim integrated 6 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
(v ccx = v ccro = v cct = 2.85v to 3.47v, v ccto = 2.97v to 3.47v, v gnd = 0v, t a = -40 c to +95 c. typical values are at v ccx = v ccro = v cct = v ccto = 3.3v, 14 single-ended load for toutc/touta, and t a = +25 c, unless otherwise noted. see figure 1 for electrical setup.) (note 2) note 2: limits are 100% tested at t a = +25c (and/or t a = +95c). limits over the operating temperature range and relevant sup - ply voltage range are guaranteed by design and characterization. note 3: guaranteed by design and characterization. note 4: a repeating 2 7 prbs + 72 zeros and 2 7 prbs (inverted) + 72 ones pattern is used. deterministic jitter is defined as the arithmetic sum of pulse-width distortion (pwd) and pattern-dependent jitter (pdj). source dj is removed from the measure - ment. note 5: v rin is 30mv p-p to 1.2v p-p differential amplitude, set_cml = 10d. input data transition time 21ps (20% to 80%). note 6: los must not assert if the input data is invalid for less than 2.3s. the los must assert, if the data is invalid for more than 80s. the signal at the input will be switched between two amplitudes signal_on, and signal_off. 1) receiver operates at sensitivity level plus 1db power penalty a) signal_off = 0; signal_on = (+8db) + 10log(min_assert_level) b) signal_on = (+1db) + 10log(max_deassert_level); signal_off = 0 2) receiver operates at overload signal_off = 0; signal_on = 1.2v p-p. note 7: los hysteresis (10 log(v los-deassert /v los-assert )db) is designed to be > 1.25db for set_los[6:0] dac code from 8d to 101d. los is characterized with a 2 23 -1 prbs pattern for 11.3gbps and a k28.5 pattern for 1.25gbps operation note 8: output of a tia in case of loss of light, see figure 7. note 9: i ld_dc = i dc + 0.5 i mod r/(50 + r), where i ld_dc is the effective laser dc current, i dc is the dc dac current, i mod is the modulation dac current, and r is the differential laser load resistance. example: for r = 5, i ld_dc = i dc + 0.045 i mod . the required compliance range for vout, while tx output is enabled, is v ccto - 1v to v ccto - 2v. parameter symbol conditions min typ max units maximum capacitive load sda, scl c b total bus capacitance on one line with 4.7k pullup from sda to v cc 20 pf 2-wire timing specifications (figure 5) maximum scl clock frequency f scl 400 khz minimum scl pulse width high t ch 1.3 s minimum scl pulse width low t cl 0.6 s minimum bus free time between stop and start condition t buf 1.3 s minimum stop setup time t su_sto 600 ns minimum start setup time t su_sta 600 ns minimum start hold time t hd_sta 600 ns minimum sda setup time t hd_dat 100 ns minimum sda hold time t hd_dat receive 0 ns transmit 300 minimum scl and sda rise and fall time t r , t f (note 15) 20 + 0.1c b ns maximum spike pulse width suppressed by input filter t sp 50 ns maximum capacitive load sda, scl c b total bus capacitance on one line 20 pf electrical characteristics (continued) maxim integrated 7 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
note 10: i ld_mod = i mod 50/(50 + r), where i ld_mod is the effective laser modulation current, i mod is the modulation dac cur - rent, and r is the differential laser load resistance. example: for r = 5, i ld_mod = 0.91 i mod . note 11: stability is defined as [(i measured ) - (i reference )]/(i reference ) over the listed current/temperature range and v cct = v ccx = v ccro = v ccref 5%, v ccref = 3.3v. reference current measured at v ccref and t ref = +25c. note 12: stability is defined as [(i measured ) - (i reference ) over the listed temperature range and supply range. reference current measured at v cc = 3.3v and t ref = +25c. note 13: calibrated at room temperature by adjusting tsns_int_ofs[15:0] (tsns_int_scl[15:0] unchanged from default value). in order to reduce the effect of self-heating the rx and tx circuitry are disabled. to minimize the reported error over the full temperature range, calibration is set such that the reported result is 2c above ambient at room temperature. in the applica - tion, self-heating may introduce additional variation. note 14: for open-drain configuration fault_pu_en = 0 and los_pu_en = 0. for cmos output configuration fault_pu_en = 1 and los_pu_en = 1. note 15: c b = total capacitance of one bus line in pf. (v ccx = v ccro = v cct = 2.85v to 3.47v, v ccto = 2.97v to 3.47v, v gnd = 0v, t a = -40 c to +95 c. typical values are at v ccx = v ccro = v cct = v ccto = 3.3v, 14 single-ended load for toutc/touta, and t a = +25 c, unless otherwise noted. see figure 1 for electrical setup.) (note 2) (v cc = 3.3v, t a = +25c, data pattern 2 31 -1 prbs, unless otherwise noted.) 10gbps optical eye diagram toc01 0 10 20 30 40 50 60 70 80 90 100 0 128 256 384 512 modulation current (ma p - p ) modreg[8:0] modulation current vs. modreg toc02 i mod assumes 5 differential laser load i ld_mod set_mod[7:0] controls modreg[8:1] 0 10 20 30 40 50 60 0 256 512 768 1024 dc dac current (ma) dcreg[9:0] dc dac current vs. dcreg toc03 i dc if apc is disabled, set_dc[7:0] controls dcreg[9:2] transmitter enable toc04 4s/div v cc = 3.3v disable optical output fault transmitter disable toc05 optical output v cc = 3.3v fault disable 1s/div frequent assertion of disable toc06 20s/div fault disable optical output mdin external fault electrical characteristics (continued) typical operating characteristics maxim integrated 8 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
(v cc = 3.3v, t a = +25c, data pattern 2 31 -1 prbs, unless otherwise noted.) response to fault toc07 2s/div fault mdin optical output external fault fault recovery toc08 4s/div fault disable optical output mdin -40 -35 -30 -25 -20 -15 -10 -5 0 100 1000 10000 100000 sdd11 (db) frequency (hz) tx input differential return loss vs. frequency toc09 m g g g -40 -35 -30 -25 -20 -15 -10 -5 0 100 1000 10000 100000 scc11 (db) frequency (hz) tx input common - mode return loss vs. frequency toc10 m g g g -40 -35 -30 -25 -20 -15 -10 -5 0 100 1000 10000 100000 sdd22 (db) frequency (hz) tx output differential return loss vs. frequency toc11 m g g g -40 -35 -30 -25 -20 -15 -10 -5 0 100 1000 10000 100000 scc22 (db) frequency (hz) tx output common - mode return loss vs. frequency toc12 m g g g 2 2.4 2.8 3.2 3.6 4 2 2.4 2.8 3.2 3.6 reported voltages (v) forced supply voltage (v) reported v ccto , v ccx , v cct voltages vs. forced supply voltage toc13 v ccto v cct v ccx 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 reported rssi current (ma) forced rssi input current (ma) reported rssi current vs. forced rssi input current toc14 -1.5 -1 -0.5 0 0.5 1 1.5 -40 -20 0 20 40 60 80 100 absolute error ( c) temperature ( c) external temperature sensor absolute error toc15 3 error bands based on 30 part characterization typical operating characteristics (continued) maxim integrated 9 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
(v cc = 3.3v, t a = +25c, data pattern 2 31 -1 prbs, unless otherwise noted.) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 -40 -20 0 20 40 60 80 100 error ( c) temperature ( c) internal temperature sensor error (23 c calibration) toc16 3 error bands 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 reported badc voltage (v) forced badc voltage (v) reported badc voltage vs. forced badc voltage toc17 200 300 400 500 600 700 800 900 1000 1100 1200 0 4 8 12 16 20 24 28 32 differential rx output amplitude (mv p - p ) set_cml[4:0] differential rx output amplitude vs. set_cml dac setting toc18 1111 0000 pattern de - emphasis disabled 1db de - emphasis 2db de - emphasis 3db de - emphasis 4db de - emphasis 0 50 100 150 200 250 0 20 40 60 80 100 120 140 differential input amplitude (mv p - p ) set_los[6:0] rx input - based los threshold vs. set_los toc19 deassert assert 1e-12 1e-11 1e-10 1e-09 1e-08 1e-07 1e-06 1e-05 1e-04 1e-03 1.5 2 2.5 3 3.5 ber input amplitude (mv p - p ) rx ber vs. differential input amplitude (10.3gbps) toc20 rx output (input: 1.0625gbps, 30mv p - p , 2 7 - 1 prbs) 80mv/div toc21 140ps/div rate_sel + rsel = 0, set_rxbw = 00 (1ghz) typical operating characteristics (continued) maxim integrated 10 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
(v cc = 3.3v, t a = +25c, data pattern 2 31 -1 prbs, unless otherwise noted.) rx output through 4.6db channel loss at 5ghz, 11.3gbps, no deemphasis 80mv/div toc25 13ps/div rx output through 4.6db channel loss at 5ghz, 11.3gbps, deemphasis = 4db 80mv/div toc26 13ps/div rx output (input: 4.25gbps, 30mv p - p, 2 7 - 1 prbs) 80mv/div toc22 35ps/div rate_set + rsel = 0, set_rxbw = 11 (3ghz) rx output (input: 10.3gbps, 30mv p - p , 2 31 - 1 prbs) 80mv/div toc23 15ps/div rate_set + rsel = 1, set_rxbw = 01 (10ghz) rx output (input: 10.3gbps, 1200mv p - p , 2 31 - 1 prbs) 80mv/div toc24 15ps/div rate_sel + rsel = 1, set_rxbw = 01 (10ghz) 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 -40 -20 0 20 40 60 80 v ccx, v cct (v) temperature ( c) por (p3vflag) assert/de - assert vs. temperature toc27 assert de - assert typical operating characteristics (continued) maxim integrated 11 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
pin name function equivalent circuit 1 intrpt interrupt output, cmos. programmable interrupt signal. v ccro intrpt esd protection max 3956 ma x 3956 tqfn 5 mm x 5 mm top view fault v ccro rout + rout - v ccro intrpt tsns vout toutc rssi touta v ccto 1 2 rin - 4 5 6 7 rin + v ccx tin - tin + i . c . regfilt disable tgnd 3 rsel sda los scl + v ccx v cct i . c . i . c . csel mdin 8 badc 16 15 14 13 12 11 10 9 17 18 19 20 21 22 23 24 26 25 27 28 29 30 31 32 pin description pin confguration maxim integrated 12 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
pin name function equivalent circuit 2 fault transmitter fault, open-drain output. a logic-high indicates a fault condition has been detected. it remains high even after the fault condition has been removed. a logic-low occurs when the fault condition has been removed and the fault latch has been cleared by the disable signal. connect fault to host v cc via a 4.7k to 10k resistor. fault can also be confgured as a cmos output requiring no external resistor by setting the fault_pu_ en bit high. fault v ccro esd protection v ccro fault _ pu _ en max 3956 3 disable transmitter disable, lvttl/cmos input. set to logic-low for normal operation. logic-high or open disables both the modulation and dc current. internally pulled up by a 7.5k resistor to v ccro . v ccro disable esd protection v ccro v ccro 7 . 5 k? max 3956 4, 7 v ccro power supply. provides supply voltage to the transceiver digital core and the rx output circuitry. 5 rout+ differential receiver data output, cml. this output has 50 terminations to v ccro . polarity is set by the rx_pol bit. 50 50 rout + rout - v ccro set _ cml esd protection max 3956 6 rout- pin description (continued) maxim integrated 13 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
pin name function equivalent circuit 8 csel chip-select input, cmos. used for 3-wire communication. setting csel to logic-high starts a cycle. setting csel to logic-low ends the cycle and resets the control state machine. internally pulled to ground by a 75k resistor. set low if using 2-wire communication. v ccro csel esd protection v ccro max 3956 75 k 9 scl serial-clock input, cmos. internally pulled to ground by a 75k resistor. v ccro scl esd protection v ccro 75 k max 3956 10 sda serial-data bidirectional i/o, cmos. open-drain output. this pin has a 75k internal pullup, but it requires an external 4.7k to 10k pullup to meet 3-wire timing specifcations. sda esd protection v ccro v ccro v ccro 75 k max 3956 pin description (continued) maxim integrated 14 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
pin name function equivalent circuit 11 regfilt internal filter node. requires 0.1f decoupling capacitor to ground. 12, 16, 26 i.c. internal connection. leave unconnected. 13 tin+ differential transmitter data input. the polarity is set by the tx_pol bit. tin + tin - v cct esd protection 50 50 v cct - 1 v max 3956 14 tin- 15 v cct power supply. provides supply voltage to the transmitter core. 17 mdin monitor diode input. connect this pin to the cathode of the monitor diode. for transmitter power monitoring mdin needs to be connected even for open- loop operation. external fltering on this pin should be optimized for each tosa confguration. the thevenin equivalent input of this pin is 40 to v cct - 1.25v. pin description (continued) maxim integrated 15 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
pin name function equivalent circuit 18 v ccto power supply. provides power to the transmitter output and laser tosa. touta toutc v ccto esd protection vout cascode 25 25 max 3956 19 touta inverting modulator current output with 25 back-termination. connect to laser anode through 25 transmission line. 20 toutc noninverting modulator current output with 25 back-termination. connect to laser cathode through 25 transmission line. 21 v out combined laser cathode current return path and sinking laser dc current output. v ccto vout max 3956 22 tgnd connect to an external temperature sensor (cathode). 23 tsns connect to an external temperature sensor (anode). tsns tgnd esd protection max 3956 v ccx pin description (continued) maxim integrated 16 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
pin name function equivalent circuit 24 rssi current input to main adc for receive- signal-strength-indication (rssi). the voltage at this pin is regulated internally to 1.62v. v ccx rssi esd protection adc 1 . 62 v max 3956 25 badc auxiliary adc input ( 1.16v full scale) 27, 30 v ccx power supply. provides supply voltage to the receiver core. 28 rin- differential receiver data input. contains 50 terminations on-chip. connect these inputs to the tia outputs using coupling capacitors. rin+ rin- v ccx v ccx - 0.1v esd protection 50 50 MAX3956 29 rin+ pin description (continued) maxim integrated 17 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
pin name function equivalent circuit 31 rsel rate select, cmos input. internally pulled to ground by a 75k resistor. pin is internally ored with rate_sel bit. the output of the or sets the rx circuitry path to 10g for logic 1, 4g for logic 0. 32 los receiver loss-of-signal (los) output, open drain. this output goes to a logic- high when the level of the input signal drops below the set_los register threshold. polarity is set by los_pol register. the los circuitry can be disabled by setting los_en = 0. pull this pin to host v cc via a 4.7k to 10k resistor. los can also be confgured as a cmos output requiring no external resistor by setting the los_pu_en bit high. los v ccro esd protection v ccro los _ pu _ en max 3956 ep exposed pad. ground. this is the only electrical connection to ground and must be soldered to circuit board ground for proper thermal and electrical performance (see the exposed-pad package and thermal considerations section). rsel v ccro esd protection 75 k v ccro max 3956 pin description (continued) maxim integrated 18 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
figure 1. ac electrical test schematic i .c. v ccro regfilt mdin v ccto touta vout tin+ disable fault intrpt scl sda csel badc 0.1f v ccx v ccro rout+ rout- tin- v cct i.c. toutc tgnd rssi tsns v ccx v ccx rin- rin+ rsel los tx_disable intrpt csel scl sda i.c. 0.01f v cct 0.01f z 0 = 50 z 0 = 50 mmbt3906 100pf 0.3pf 39 100 ferrite bead 2.2h 2.2h 100 0.1f 0.1f 16 40.2 0.01f 0.01f z 0 = 50 z 0 = 50 v ccx v ccx 0.1f 0.1f 0.01f z 0 = 50 z 0 = 50 vout 0.01f 0.01f 0.1f v ccto 5 100pf rssi badc 10 10pf z 0 =50 z 0 =50 z 0 = 25 z 0 = 25 16 vout rsel los fault v ccx 40.2 ferrite bead 0.01f 0.01f MAX3956 10pf 0.01f 0.01f 0.1f 0.1f + 0.01f 0.01f maxim integrated 19 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
figure 2. functional diagram v ccro 50 50 rin+ rin- v ccx - 0. 1v los rout+ rout- 1.25gbps to 11. 3gbps dual path limiting amplifier squelch regfilt disable fault v ccto touta toutc vout laser safety and control apc mdin mdin tx power monitor bias monitor laser driver equalizer tx los detector tin+ tin- configurable 2-wire / 3 -wire interface with interrupt signal generation register map intrpt csel sda scl v ccx v cct v ccto 12 -bit adc tsns tgnd badc rssi 1. 25 gbps to 11. 3gbps dc- coupled laser driver 4g 10 g mux communication and digital diagnostics and monitoring offset cancellation rx los with debouncing v_rssi control external temp sensor internal temp sensor ? 4 ? 4 ? 4 i / v 16 bits 16 bits 12 bits, fs = 4. 656 v 12 bits, fs = 4. 656 v 12 bits, fs = 4. 656 v 16 bits, fs = 2. 32 ma 12 bits, fs = 1. 164 v rsel internal regulator max 3956 1g - 4g 50 50 v cct C 1v 50 50 ext temp : int temp : v ccx : v cct : v ccto : rssi : badc: maxim integrated 20 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
detailed description the MAX3956 combines a high-gain limiting amplifier, laser driver, and digital diagnostics monitoring (ddm). the limiting amplifier includes offset cancellation, pro - grammable signal detect threshold, selectable bandwidth, and deemphasis. the laser driver includes automatic power-control (apc), laser current and power measure - ment capability, overcurrent limiting, and fault detection. a serial control interface enables an external controller to set all parameters necessary for operation and read all monitors and status indicators. the interface accepts either 2 - wire or 3-wire protocol. the features and performance are specifically designed to be compatible with low-cost microcontrollers to provide complete sff-8472 functionality, including laser fault detection, diagnostics, and automatic power control. the MAX3956 includes all the logic required for laser protec - tion, control loop operation, and monitor diode (md) cur - rent measurement. 1.25gbps to 11.3gbps limiting amplifer block description limiting amplifer the limiting amplifier consists of a multistage-multipath amplifier, offset-correction circuit, loss-of-signal circuit, and output buffer. its low noise and high gain optimize optical performance. configuration options (los thresh - old, los polarity, output amplitude, output deemphasis, and data polarity) enhance layout flexibility and rosa compatibility. high-speed input signal path the inputs, rin, have an internal 100 differential termi - nation and should be ac-coupled to the transimpedance amplifier. offset cancellation the offset cancellation loop compensates for pulse-width distortion at rin and internal offsets. the default small- signal low-frequency cutoff of the offset cancellation loop is 10khz when az_bw[1:0] is set to 01. loss-of-signal circuitry (los) the loss-of-signal circuitry detects the amplitude of the incoming signal and compares it against a programmable threshold, which is controlled by set_los[6:0]. the range of los assert is 10mv p-p to 121mv p-p . changing the los threshold during operation (i.e., without execut - ing a reset) does not cause a glitch or incorrect los out - put. the detector has 2db of hysteresis to control chatter at the los output. the los output polarity is controlled by the los_pol bit. the entire los circuit block can be disabled by setting los_en = 0. output drivers the rout outputs are terminated with 50 to v ccro . the differential output level can be programmed between 400mv p-p and 1000mv p-p by the set_cml[4:0], and the output polarity can be inverted. the output can be disabled to its common-mode voltage either manually or automatically by an los condition (squelch through the sq_en bit). deemphasis may be enabled to compensate for fr4 losses with a 10gbps signal. if enabled, settings of 1db, 2db, 3db, and 4db deemphasis are available. 1.25gbps to 11.3gbps laser driver block description the laser driver consists of a high-speed differential input buffer, selectable input equalizer, polarity switch buffer, laser modulator and dc current generator, monitor diode input buffer with adjustable gain, apc loop circuitry, eye- safety monitors, and disable pin. differential high-speed input buffer with program - mable equalization the tin inputs are internally biased and have a 100 differential termination. the first amplifier stage features a programmable equalizer, controlled by tx_eq, to com - pensate for high-frequency losses including the sfp con - nector. the tx_pol bit controls the signal path polarity. an active ac input signal is indicated by tin_los. laser modulator and dc generator the laser modulator provides dc-coupled current into the cathode of the laser diode at the toutc pin. the modulation current amplitude is set by modreg[8:0]. the modulation current dac guarantees modulation amplitudes up to 85ma. the instantaneous compliance voltage for toutc is 0.6v to v ccto - 1v and for touta is v ccto 1v. the vout pin sinks dc current from the lasers cathode. the amplitude of the laser dc current is controlled by dcreg[9:0]. the laser dc current dac guarantees val - ues up to 57ma. monitor diode current input buffer the mdin input stage has adjustable gain settings, allow - ing a large input signal range. the mdin_gain[2:0] bits set the transimpedance gain from 156 to 2496 in one octave steps. maxim integrated 21 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
automatic power control circuitry (apc) the MAX3956 contains circuitry to maintain constant optical power using feedback from the monitor diode. the set_apc register in conjuction with mdin_gain controls the set point for average laser power when apc operation is enabled. ddm digital diagnostics and monitoring is provided on the MAX3956. this includes internal and external tempera - ture monitoring, tx dc current reporting, tx average current reporting, tx output power reporting, rssi, and internal supply voltage monitoring. the MAX3956, when combined with a digital-only c, will provide compli - ance with sff-8472 (diagnostic monitoring interface for optical transceivers). 3-wire interface the MAX3956 implements a proprietary 3-wire digital slave interface. the 3-wire interface consists of an sda bidirectional data line, an scl clock signal input, and a csel chip-select input (active high). the external master initiates a data transfer by asserting the csel pin then generating a clock signal. all data transfers are most sig - nificant bit (msb) first. see figure 3 for more information. protocol each single register operation consists of 16-bit transfers (15-bit address/data, 1-bit rwn). the bus master gener - ates 16 clock cycles to scl. all operations transfer 8 bits to the MAX3956; the rwn bit determines if the cycle is read or write. see table 1. write mode (rwn = 0) writing to a register requires two transactions: a write of 12h to the modectrl register to enter setup mode, followed by a write to the target address. for each trans - action, the master generates 16 clock cycles at scl. it outputs a total of 16 bits (msb first) to the sda line at the falling edge of the clock. the master closes the transmis - sion by setting csel to 0. figure 3 shows the 3-wire interface timing. read mode (rwn = 1) the master generates 16 clock cycles at scl in total. the master outputs a total of 8 bits (msb first) to the sda line at the falling edge of the clock. the sda line is released after the rwn bit has been transmitted. the slave outputs 8 bits of data (msb first) at the rising edge of the clock. the master closes the transmission by setting csel to 0. figure 3 shows the 3-wire interface timing. figure 3. 3-wire digital interface timing diagram table 1. 3-wire digital communication word structure bit name description 15:9 address 7-bit internal register address 8 rwn 0: write; 1: read 7:0 data 8-bit read or write data csel scl sda csel scl sda 1 2 3 4 5 6 7 8 a6 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 a5 a4 a3 a2 a1 rwn d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 rwn write mode read mode a0 a6 a5 a4 a3 a2 a1 a0 t l t l t ch t cl t ds t dh t ch t cl t ds t d t dh t t t t maxim integrated 22 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
block write mode (rwn = 0) the two different block write modes of operation are described in table 2. block read mode (rwn = 1) the master initiates the block read mode by accessing any register address and setting the rwn bit to 1. the block read mode starts by stretching the csel interval beyond the 16 clock cycles, and it is exited automatically when the master has set csel to 0. mode control the MAX3956 contains more than 128 registers, which exceeds the addressability of a 7-bit number. so it has two pages (page 0 and page 1) that contain all the regis - ters. to write to or read from either page, the page must first be selected by writing to the modectrl register: 81h to access page 0, 55h to access page 1. once a page has been selected any further writes or reads will access that page until the modectrl is written to the new page. the default page upon por is page 1. setup mode allows the master to write data into any regis - ter except the status registers and read-only registers. to enter the setup mode, 12h is written to the modectrl register. the next operation is unrestricted to any writable register. the setup mode is automatically exited after the next operation is finished. this sequence must be repeated if further register writes are necessary. to speed up the laser control by a factor of 2, the modinc, dcinc, and apcinc registers can be updated without writing setup mode to modectrl. fault-clear mode allows the clearing of the fault latch, and restarts operation of the device. it is activated by writing 68h to the modectrl register. table 2. block write examples figure 4. recommended 3-wire implementation using a generic microcontroller table 3. modectrl register settings block write mode 1 (starts at address h0x01) block write mode 2 (starts at any address) master sets csel to 1 master sets csel to 1 addr h0x00 + rwn = 0 addr h0x00 + rwn = 0 data 81h (page 0 access) C or data 55h (page 1 access) data 81h (page 0 access) C or data 55h (page 1 access) master sets csel to 0 master sets csel to 0 master sets csel to 1 master sets csel to 1 addr h0x00 + rwn = 0 addr h0x00 + rwn = 0 data 12h (setup mode) data 12h (setup mode) data 1 (addr h0x01) master sets csel to 0 data 2 (addr h0x02) master sets csel to 1 data 3 (addr h0x03) addr h0x0n + rwn = 0 data 1 (addr h0x0n) data j (addr h0xj) data 2 (addr h0x0n + 1) master sets csel to 0 data 3 (addr h0x0n + 2) data i (addr h0xn + i - 1) master sets csel to 0 code (hex) condition 00 normal mode 12 setup mode 55 select page 1 mode 68 fault clear mode 81 select page 0 mode v ccro 75 k c 2 . 2 k scl sdo sdi csel scl sda csel 75 k 75 k max 3956 maxim integrated 23 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
2 - wire communication 2 - wire defnition the following terminology is commonly used to describe 2 - wire data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the masters request. bus idle or not busy : time between stop and start conditions when both sda and scl are inactive and in their logic-high states. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low, while scl remains high, generates a start condition. see figure 5 for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high, while scl remains high, generates a stop condition. see figure 5 for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data trans - fer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a spe - cific register address to begin a data transfer. a repeated start condition is issued identically to a normal start condition. see figure 5 for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements (figure 5). data is shifted into the device during the rising edge of the scl. bit read: at the end a write operation, the master must release the sda bus line for the proper amount of setup time before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses, including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowl- edgement (ack) or not-acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmit - ting a zero during the 9th bit. a device performs a nack by transmitting a one during the 9th bit. timing for the ack and nack is identical to all other bit writes (figure 5). an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the master are done according to the bit write definition and the acknowledge - ment is read using the bit read definition. figure 5. 2-wire timing diagram scl note: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low maxim integrated 24 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the mas - ter must nack the last byte read to terminate communi - cation so the slave returns control of sda to the master. slave address byte: each slave on the 2 - wire bus responds to a slave address byte sent immediately following a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the MAX3956 responds to the slave address 46h. the part contains more than 128 registers, which exceeds the addressability of a 7-bit number. so it has two pages (page 0 and page 1) that contain the registers. to write to or read from either page, the page must first be selected by writing to the modectrl register: 81h to access page 0, 55h to access page 1. once a page has been selected any further writes or reads will access that page until modectrl is written with a new page. the default page upon por is page 1. 2 - wire protocol see figure 6 for an example of 2 - wire timing. writing a single byte to the MAX3956: the master must generate a start condition, write the slave address byte, write r/ w = 0, write the modectrl address, write 12h (setup), and generate a stop condition. this pre - pares the MAX3956 for a write. then the master must generate a start condition, write the slave address byte, write r/ w = 0, write the register address, write the byte of data, and generate a stop condition. remember that the master must read the slaves acknowledgement during all byte write operations. figure 6. example 2-wire timing typical 2-wire write transaction start 1 0 0 0 1 1 0 msb lsb slave ack b7 b 6 b 5 b 4 b 3 b 2 b 1 msb b 0 lsb slave address = 46h read/ write register address slave ack b 7 b 6 b 5 b 4 b 3 b 2 b 1 msb b 0 data slave ack stop lsb example transactions start slave ack 10001100 b ) single-byte write - write 10h to h0x14 slave ack start {46h,0} slave ack 10001100 a ) set access to page 1 modectrl slave ack 00000000 01010101 page 1 = 55h slave ack stop start slave ack 10001100 h 0x14 00010100 slave ack setup = 12h slave ack stop 10h slave ack stop modectrl 00000000 00010010 00010000 c ) single-byte read - read register h0x21 start slave ack 10001100 slave ack h0x21 master nack stop 00100001 data in 21h repeated start {46h,1} 10001101 r/w start slave ack 10001100 d ) two-byte write - write 92h and 93h to h0x14 and h0x15 slave ack start slave ack 10001100 h 0x14 00010100 slave ack setup = 12h slave ack stop 92h slave ack stop modectrl 00000000 00010010 93 h 10010010 10010011 e ) two-byte read - read h0x22 and h0x23 start slave ack 10001100 slave ack h0x22 master nack stop 00100010 data in 22h repeated start 10001101 master ack data in 23h data data slave ack ? the MAX3956 device address is 46h ? there are two register pages. once access has been set to page 0 or page 1, any further read or writes will access that page. the default page at por is page 1. data written data read {46h,0} {46h,0} {46h,0} {46h,0} {46h,0} {46h,0} {46h,1} read/write bit address maxim integrated 25 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
writing multiple bytes to the MAX3956: to write mul - tiple bytes to a slave, the master must generate a start condition, write the slave address byte, write r/ w = 0, write the modectrl address, write 12h (setup), and generate a stop condition. then the master must gener - ate a start condition, write the slave address byte, write r/ w = 0, write the register address, write multiple data bytes, and generate a stop condition. the device writes multiple bytes with this second write transaction. this is internally controlled by an address counter that allows data to be written to consecutive addresses without trans - mitting a register address before each data byte is sent. the address counter limits the write to one page. for example: a 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three con - secutive addresses. the result is that addresses h0x06, h0x07, h0x08 would contain 11h and 22h, and 33h respectively. the apcinc, modinc, and dcinc registers are the only registers in the device that do not require 12h (setup) to be written to modectrl before writing to these regis - ters. this allows quicker adjustments of these registers. writing to the apcinc, modinc, or dcinc register : the master must generate a start condition, write the slave address byte, write r/ w = 0, write the address, write the byte of data, and generate a stop condi - tion. remember that the master must read the slaves acknowledgement during all byte write operations. design procedure load factory calibration constants upon power-up, after por has deasserted, the microcon - troller must load the individually programmed calibration constants into the calibration registers. this is accom - plished by five write commands shown below: write: 55h to h0x00 write: 34h to h0x00 write: 01h to h0x7a write: 34h to h0x00 write: 03h to h0x7a power-on-reset (por) a power-on-reset circuit provides proper startup sequenc - ing and ensures that the laser is off while the supply volt - age is ramping or below a specified threshold ( 2.55v). the serial interface can also be used to command a manual reset at any time by setting soft_reset = 1, which is identical to a power-on reset. when using soft_ reset, the MAX3956 transmitter must first be disabled, either by the disable pin, by setting tx_en = 0, or by setting xcvr_en = 0. either power-on or soft_reset requires approximately 150s to complete. por sets all figure 7. limiting amplifier block diagram 50 50 los 50 50 de-emphasis rin+ rin- rout+ rout- los v ccro set_cml set_rxde rx_pol az_bw set_los los_masktime v ccx - 0.1v mux high b/w low b/w offset correction rsel rate_sel set_rxbw rx_rate maxim integrated 26 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
registers to their defaults. the recommended por proce - dure is as follows: ? because the por is routed to both the fault and intrpt pins, the c should monitor one of these for por detection in the case of a power-supply brown- out issue. ? if fault is used by the c to detect a MAX3956 por event, a pullup resistor should be used on this pin. this is because fault defaults to open drain upon por. ? upon por event detection, the controller initiates 2 - wire or 3-wire communication with MAX3956 by repeatedly reading out the topstat register until the 1-to-0 transition occurs for both pord and p3vflag. ? once the por flags have cleared, repeatedly read the txstat1 register until the tx status flags have cleared. write a fault clear (68h) to the modectrl register to clear any startup related faults. ? controller writes commands to load calibration con - stants into calibration registers then writes/initializes all applicable registers. 1.25gbps to 11.3gbps receiver details figure 7 is a block diagram of the MAX3956 receiver cir - cuitry. it includes the offset-correction block, los block, high-bandwidth/low-bandwidth paths, input and output stages, and output deemphasis. offset-correction circuitry the offset-correction circuitry is provided to remove pwd at rin and offsets caused by intrinsic mismatch within the amplifier stages. the bandwidth of the offset-correc - tion loop is adjustable and is set by az_bw[1:0]. table 4 shows the small-signal cutoff frequency for each setting. los circuitry the los block detects the differential amplitude of the input signal and compares it against a preset threshold controlled by the 7-bit set_los register. the los assert threshold is approximately 1.2mv p-p set_los[6:0]. the los deassert level is approximately 1.6 times the assert level to avoid los chatter. the recommended minimum setting is set_los[6:0] = 8d. los output masking the los output masking feature masks false input sig - nals that can occur after a loss-of-light event in a fiberop - tic link. these false input signals, caused by some tran - simpedance amplifier implementations, can corrupt the los output and cause system-level link diagnostic errors. the los output masking time can be programmed from 0 to 4.6ms in 36s steps using the los_masktime[6:0] register. the output mask timer is initiated on the first 0 to 1 los signal transition and prevents any further changes in the los output signal until the end of the programmed los timing period. the los output mask - ing time should be carefully chosen to extend beyond any expected input glitch. see figure 8. figure 8. los output masking table 4. offset-correction loop cutoff frequency az_bw[1:0] cutoff frequency (khz) 00 5 01 10 (default) 10 20 11 40 rin from tia raw los los debounced los _ masktime period 50 s typical rin crosses los assert threshold rin crosses los deassert threshold maxim integrated 27 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
receiver path selection and bandwidth modes table 5 shows the settings for the receiver paths and bandwidth selection modes. rx output stage the cml output is optimized for a differential 100 load and can be squelched to its common-mode voltage manually or by the internal los status. table 6 shows the output modes for various conditions/settings. deemphasis is included to compensate for fr4 loss at 10gbps and is set by the set_rxde[2:0] bits. figure 9 illustrates the effects of deemphasis on the output waveform. figure 9. deemphasis effect on rout signal table 5. receiver path selection and -3db bandwidth setting modes table 6. rout enable/disable mode table 7. rout amplitude range and resolution (typical, rsel + rate_sel = 1) rsel + rate_sel set_rxbw[1:0] output operation mode description 0 00 low-bandwidth rx path with small-signal bandwidth of 1ghz 0 01 low-bandwidth rx path with small-signal bandwidth of 2ghz 0 10 low-bandwidth rx path with small-signal bandwidth of 2.5ghz 0 11 low-bandwidth rx path with small-signal bandwidth of 3ghz 1 xx high-bandwidth rx path xcvr_en rx_en rx_out_en sq_en output operation mode description 0 x x x disabled, to v ccro 1 0 x x disabled, to v ccro 1 1 0 x output squelched, to common-mode 1 1 1 0 enabled 1 1 1 1 squelch mode controlled by los set_rxde[2:0] differential output amplitude (mv p-p ), v amp in figure 9 set_cml[4:0] = 12d set_cml[4:0] = 31d 0xx 650 1080 100 610 1000 101 570 940 110 530 850 111 480 790 v peak v amp set _ rxde = 100 set _ rxde = 101 set _ rxde = 110 set _ rxde = 111 rout + rout - not to scale . for illustrative purposes only . maxim integrated 28 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
1.25gbps to 11.3gbps laser driver the MAX3956 contains a dc-coupled laser driver designed to drive 5 to 10 tosas from 1.25gbps to 11.3gbps. it contains an input buffer with programmable equalization, dc current and modulation current dacs, output driver, and eye safety circuitry. a 2 - wire or 3-wire digital interface is used to control these functions. programmable input equalization when operating at 10gbps, connector and fr4 losses can be significant enough to increase jitter. to compen - sate for these losses the MAX3956 has adjustable input equalization as shown in table 8. when tx_eq 00, the equalizer has an optimized range of 190mv p-p to 700mv p-p differential at tin. laser dc current dac the dc current from the MAX3956 is optimized to provide up to 57ma of dc current into a 5 to 10 laser load with 58.5a resolution. the current is controlled through the 2-wire or 3-wire interface using the apc loop or by open- loop control. while the transmitter is enabled, the compli - ance voltage at vout is v ccto - 1v to v ccto - 2v. effective dc current seen by the laser (i bias ) is actually the combination of the dc dac current generated by the dcreg register (i dc ), modreg register (i mod ) and laser load (r). it is calculated by the formula: i dc dc dac current i dc = (dcreg[9:0] + 12) 58.5a i ld_dc = i dc + 0.5 i mod r/(50 + r) i bias = i ld_dc + i ld_mod /2 if the written value of dcreg[9:2] exceeds dcmax[7:0], the dc_ovfl warning flag is set and dcreg[9:2] remains unchanged. if an attempt is made to set the dcreg to be less than 0, an underflow warning bit, dc_udfl will flag. apc operation the automatic power control loop (apc) automatically adjusts dc laser current to maintain constant average current at the mdin pin. the desired average current at the mdin pin is set by the set_apc register in conjunc - tion with the mdin_gain value. the MAX3956 measures the high peak and low peak of the mdin current which represent the p1 and p0 levels of the optical power. these levels are held in the md1reg and md0reg reg - isters respectively. the apc loop will increase/decrease dc laser current to make the following equation true: set_apc[7:0] = md1reg[15:8] + md0reg[15:8] when the apc loop is closed, the average mdin current will be related to set_apc and mdin_gain by the fol - lowing equation: i mdin_avg = set_apc[7:0] 1.22mv/mdin_gain the largest step size the apc circuitry can apply to dcreg[9:0] is determined by dcinc[4:0]. so if dcinc = 1 then the apc can only increase or decrease dcreg[9:0] by 1 lsb per loop calculation. if dcinc[4:0] = 0, then the apc loop is frozen. flowchart for setting up apc operation figure 10 explains the procedure for setting up apc operation on the MAX3956 and figure 11 shows the opti - cal power for each step in the flowchart process. open loop control of dc laser current to control the dc dac current manually (not using the apc loop), the apc_en bit must be set to 0. dcreg controls the dc dac current. dcreg cannot be directly written to but can be adjusted by writing to dcinc or set_dc (if ibupdt_en=1). setting ibupdt_en = 1 allows writes to set_dc[7:0] to automatically transfer to dcreg[9:2]. the 2 lsb (bits 1 and 0) of dcreg are initialized to zero after por and can be updated using the dcinc register. the dcmax register limits the maximum dcreg[9:2] dac code. after initialization, the value of the dcreg register should be updated using the dcinc register. this optimizes cycle time and enhances laser safety. the dcinc[4:0] contains increment information in twos complement nota - tion. increment values range from -16 to +15 lsbs. laser modulation current dac the modulation current from the MAX3956 is optimized to provide up to 85ma of modulation current into a 5 laser load with 234a resolution. the modulation current is controlled through the 2-wire/3-wire digital interface using the set_dc, modmax, and modinc. effective modula - tion current seen by the laser is actually the combination table. 8 tx input equalization control tx_eq boost at 5.1ghz (db) 00 1.5 01 3 10 4.5 11 5.5 maxim integrated 29 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
figure 10. apc setup flowchart enable transmitter xcvr_en = 1 tx_en = 1 disable pin = low apply data to tin begin apc setup set apc configuration apc _ en = 1 mdin _ gain = 1 xx ( max gain ) set _ apc [ 7 : 0 ] = 128 d autorng _ en = 0 dcmax = ( user value ) dcinc > 0 p opt _ m C p opt _ t < - 0 . 1 db increase set_apc p opt _ m C p opt _ t reduce set_apc > 0 . 1 db is set_apc 64d? the monitor diode gain is too low for proper operation . yes no > 0.1db is set_apc = 255d? yes p opt_m C p opt_t no the monitor diode gain is too high for proper operation. < - 0 . 1 db average optical power set < 0 . 1 db > -0.1db within 0 . 1 db measure optical power no measure optical power measure optical power p opt_m < p opt_t - 1.5db reduce mdin_gain setting by 1 auto-ranging disabled to allow tracking error compensation lut for set_apc p opt_m = measured optical power (dbm) p opt_t = target optical power (dbm) yes maxim integrated 30 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
figure 11. example of optical power during apc setup target power optical power +2db -2db -4db -6db -8db power up mdin_gain reduced mdin_gain reduced mdin_gain reduced set_apc reduced mdin_gain = 2496 set_apc = 128d mdin_gain = 1248 set_apc = 128d mdin_gain = 624 set_apc = 128d mdin_gain = 312 set_apc = 128d mdin_gain = 312 set_apc = 102d 1.5db 0.2db maxim integrated 31 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
of the dac current generated by the set_mod register (i mod ) and laser load (r). it is calculated by the formula: i mod mod dac current i mod = (set_mod[8:0] + 16) 234a i ld_mod = i mod 50/(r laser + 50) control of laser modulation current dac modreg controls the modulation dac current and can - not be written to directly, but it can be adjusted by writing to modinc or set_mod (if imupdt_en=1). setting imupdt_en = 1 allows writes to set_mod[7:0] to auto - matically transfer to modreg[8:1]. the lsb of modreg is initialized to zero after por and can be updated using the modinc register. the modmax register limits the maximum modreg[8:1] dac code. modinc usage after initialization the value of the set_mod dac regis - ter should be updated using the modinc register to opti - mize cycle time and enhance laser safety. the modinc register is an 8-bit register where the first 5 bits contain the increment information in twos complement notation. increment values range from -16 to +15 lsbs. if the updated value of set_mod[8:1] exceeds modmax[7:0], the mod_ovfl warning flag is set and set_mod[8:1] remains unchanged. if an attempt is made to set the overall modulation dac code to be less than 0 by using a combination of set_mod register and modinc register it will cause an underflow warning bit mod_udfl. eye safety and output control circuitry there are several fault indicators associated with certain pins on the MAX3956, see figure 13. if the voltage at the pin can cause an eye safety concern, then a fault is cre - ated and the tx output can be shut off. there is also a status indicator bit associated with each kind of fault con - dition. the MAX3956 has the capability to keep the trans - mitter active even if there is a fault condition by masking that fault condition. the status register bits will always flag a fault condition even if the actual fault is masked. when the fault is masked the fault pin voltage remains low even when there is a fault condition. ddm the MAX3956 integrates the monitoring functions required to implement an sfp system, and when combined with a simple digital-only c the system can comply with the sff- 8472 msa. it may be desirable for the c to implement averaging of the ddm results. table 10 indicates the adc registers related to ddm. transceiver temperature the MAX3956 reports both the internal die temperature as well as the external board temperature (requires dis - crete pnp for sensing). either may be used to support ddm reporting, however the internal die temperature is subject to self-heating. programmable scale and offset factors allow the user to fine-tune the reported results. figure 14 shows how the scale and offset are applied to the raw temperature data. the MAX3956 reporting format is consistent with the sff-8472 reporting requirements. figure 12. laser current graph optical power laser current p 1 p 0 p avg i bias i ld _ mod i ld _ dc laser p vs . i curve optical eye diagram maxim integrated 32 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
figure 13. eye safety circuitry toutc touta v ccto i dc txstat 1 [ 0 ] tx _ dis _ copy [ 1 ] lv _ vout [ 2 ] lv _ toutc [ 3 ] lv _ touta [ 5 ] tin _ los [ 7 ] lvflag vout i mod v ccto 2 . 55 v 70 mv p - p differential tin 0 . 4 v cascode 25 25 v ccto - 2 . 53 v v ccto - 1 . 6 v v cct 2 . 55 v reset [ 0 ] mdin _ shrt mdin [ 4 ] mod _ ovfl [ 6 ] dc _ ovfl [ 7 ] mdin _ open modreg dcreg pg . 1 ; h 0 x 21 txstat 2 pg . 1 ; h 0 x 22 mdin sense logic max 3956 maxim integrated 33 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
table 9. circuit response to single-point faults pin name short to v cc short to gnd open 1 intrpt no effect (note 12) no effect (note 12) no effect (note 12) 2 fault no effect (note 12) no effect (note 12) no effect (note 12) 3 disable tx output is off if dis_pol = 1 (default). no effect if dis_pol = 0 no effect if dis_pol = 1 (default). tx output is off if dis_pol = 0 tx output is off if dis_pol = 1 (default). no effect if dis_pol = 0 4, 7 v ccro no effect board supply collapsed (note 3) no effect (note 15) 5 rout+ no effect (note 12) no effect (note 12) no effect (note 12) 6 rout- no effect (note 12) no effect (note 12) no effect (note 12) 8 csel no effect (note 12) no effect (note 12) no effect (note 12) 9 scl no effect (note 12) no effect (note 12) no effect (note 12) 10 sda no effect (note 12) no effect (note 12) no effect (note 12) 11 regfilt por on disabled no effect (note 12) 12, 16, 26 i.c. no effect no effect no effect 13 tin+ no effect depending on tin- amplitude (note 16) no effect depending on tin- amplitude (note 16) no effect depending on tin- amplitude (note 16) 14 tin- no effect depending on tin+ amplitude (note 16) no effect depending on tin+ amplitude (note 16) no effect depending on tin+ amplitude (note 16) 15 v cct no effect board supply collapsed (note 3) por on 17 mdin no effect (note 16) no effect (note 16) no effect (note 16) 18 v ccto no effect lvflag fag asserted, laser diode is off (note 16) l vflag fag asserted, laser diode is off (note 16) 19 touta no effect disabled (note 16) laser modulation current is reduced or disabled (note 16) 20 toutc laser diode is off disabled (note 16) laser modulation current is reduced or disable (note 16) 21 vout i dc is on, but not delivered to laser; no fault. disabled (note 16) disabled (note 16) 22 tgnd no effect no effect no effect 23 tsns no effect no effect no effect 24 rssi no effect no effect no effect 25 badc no effect no effect no effect 27, 30 v ccx no effect board supply collapsed (note 14) no effect (note 15) 28 rin- no effect no effect no effect 29 rin+ no effect no effect no effect 31 rsel no effect no effect no effect 32 los no effect no effect no effect ep board supply collapsed (note 14) no effect por on note 12: normal operationdoes not affect the laser power. note 13: pin functionality might be affected, which could affect laser power/performance. note 14: supply-shorted current is assumed to be primarily on the circuit board (outside this device) and the main supply is collapsed by the short. note 15: redundant path. normal in functionality but performance could be affected. note 16: depending on mask settings this condition can create a fault and shut down the tx output. default mask settings used for table 9. warning: shorted to v cc or shorted to ground on some pins can violate the absolute maximum ratings . maxim integrated 34 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
the external temperature may be measured using a dis - crete pn junction. the mmbt3906 pnp transistor is rec - ommended. for measuring temperatures above +85c, the bf550 pnp transistor is recommended. during normal operation a current is sourced from the tsns pin and tgnd is internally shorted to ground, so that the base- emitter voltage of the pnp transistor can be measured and the temperature calculated (see figure 15). the MAX3956 automatically removes the effect of parasitic resistance in series with the sense diode, allowing flex - ibility in the placement of the diode. internally measured supply voltage the MAX3956 reports the voltages of the v ccx , v cct , and v ccto pins. the result from the MAX3956 is not formatted per sff-8472 requirements, so the c must format the data. the supply voltage results are 12 bits, with a full-scale range of 4.656v. sff-8472 specifies that the supply volt - age be reported as a 16-bit number with lsb = 100v, so the result of the MAX3956 must be scaled by 1.137mv/ 100v = 11.37 in the c. tx dc current the transmit dc value, ddm_txrpt[11:0], is a calcula - tion based on the laser dc current and the laser modula - tion current. due to the laser and external tuning network, a small portion of the modulation adds to the dc current. it is shown as i ld_dc in figure 12. this value is located in the ddm_txrpt[11:0] register (when ddm_txrpt_ sel is set to 0) and is calculated as: tx dc current = ddm_txrpt[11:0] = i dc + i mod /12.8 where: i dc = (dcreg[9:0] + 12) 58.5a i mod = (modreg[8:0] + 16) 234a the lsb size of ddm_txrpt[11:0] is 58.5a. the maximum value of ddm_txrpt[11:0] is 1199d (70.1ma), while the minimum value is 17d (1ma). note: the register ddm_txrpt[11:0] can take on the value of tx dc or tx average. to select tx dc, set the ddm_txrpt_sel bit to 0. when the ddm_tx_shdn bit is high, the ddm_txrpt values (whether tx dc or tx average) are invalid and held at last value before the transmitter was disabled. this includes disable by means of por, fault, disable pin, tx_en = 0, or xcvr_en = 0. tx average current the transmit average current is a calculation based on the laser dc current and the laser modulation current. it is shown as i bias in figure 12. this value is located in the ddm_txrpt[11:0] register (when ddm_txrpt_sel is set to 1) and calculated as: tx average current = ddm_txrpt[11:0] = i dc + 0.484 i mod where, i dc = (dcreg[9:0] + 12) 58.5a i mod = (modreg[8:0] + 16) 234a figure 14. ddm temperature scale and offset raw external temperature data ddm _ ext tsns [ 15: 0 ] scale tsns _ ext _ scl [ 15: 0 ] d 25636 d tsns _ ext _ ofs [ 15:0 ] d 128d - offset raw internal temperature data ddm _ int tsns [ 15: 0 ] scale tsns _ int _ scl [ 15: 0 ] d 25843 d tsns _ int _ ofs [ 15:0 ] d 128d - offset maxim integrated 35 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
note 17: read both the upper and lower registers in a single block read. note 18: unsigned result. note 19: unsigned result. results for negative inputs will be clamped to 00h. note 20: upper byte is signed twos complement (-128 to +127), and lower byte is unsigned fractional (0 to 255/256). note 21: the result may be toggled between laser dc current and laser average current using the ddm_txrpt_sel bit. the lsb size of ddm_txrpt[11:0] is 58.5a. the maxi - mum value of ddm_txrpt[11:0] is 2055d (120.2ma), while the minimum value is 43d (2.5ma). note: the register ddm_txrpt[11:0] can take on the value of tx dc or tx average. to select tx average, set the ddm_txrpt_sel bit to 1. when the ddm_tx_shdn bit is high, the ddm_txrpt values (whether tx dc or tx average) are invalid and held at last value before the transmitter was disabled. this includes disable by means of por, fault, disable pin, tx_en = 0, or xcvr_en = 0. tx output power the transmit power register value, ddm_txp[11:0], is a measure of the monitor diode current at the mdin pin. to convert the register value to the actual tx power, use the following equation: p avg = (ddm_txp[11:0] 977na)/k md where k md is the laser diode to monitor diode gain in a/w. the ddm_txp value is updated when the automat - ic power control adc completes its averaging of 32 (mdavg_cnt=0) or 256 (mdavg_cnt=1) samples. these samples occur every 100ns while the transmitter is on, so ddm_txp updates occur at every 256 100ns = 25.6s when mdavg_cnt=1. the maximum value of ddm_txp[11:0] is 4080d, while the minimum value is 32d. rx optical power the MAX3956 reports the rssi input current. the con - version between rssi current and input optical power must be handled within the c. for pin diode receivers a simple linear scaling factor may be all that is needed to convert between rssi current and optical power. rssi interface the rssi pin is an adc input used to measure rssi current from the tia. for optimum power-supply rejection it is recommended to connect 100pf in series with 5 between the rssi pin and gnd. the rssi pin voltage is regulated to 1.62v as shown in figure 16. the input stage is designed to only sink table 10. ddm register descriptions (note 17) raw adc parameter upper register lower register bits update rate lsb size notes ddm_avg off (1x) on (4x) vccx ddm_vccx[11:8] ddm_vccx[7:0] 12 10ms 40ms 1.137mv 18 vcct ddm_vcct[11:8] ddm_vcct[7:0] 12 10ms 40ms 1.137mv 18 vccto ddm_vccto[11:8] ddm_vccto[7:0] 12 10ms 40ms 1.137mv 19 badc ddm_badc[11:8] ddm_badc[7:0] 12 10ms 40ms 284.2v 19 rssi ddm_rssi[15:8] ddm_rssi[7:0] 16 10ms 40ms 35.5na 19 internal temperature ddm_int_tsns[15:8] ddm_int_tsns[7:0] 16 10ms 40ms 1/256c 20 external temperature ddm_ext_tsns[15:8] ddm_ext_tsns[7:0] 16 10ms 40ms 1/256c 20 tx dc tx average ddm_txrpt[11:8] ddm_txrpt[7:0] 12 26s 58.48a 21, 22 tx power ddm_txp[11:8] ddm_txp[7:0] 12 26s 977na 21 maxim integrated 36 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
current. the rssi will flag an interrupt (ddm_rssi_lo_ fail) if current is pulled out of this pin. signal loopback for testing purposes, the tx input signal can be routed to the rx output (tin to rout). likewise, the rx input signal can be routed to the laser output (rin to touta/ toutc). when engaging loopback of tin to rout, be aware that if rx squelching is enabled there needs to be an active signal at rin for rout to be enabled. similarly, if the tx squelch mode is enabled, there needs to be a signal at tin for touta/toutc to be enabled. see figure 17. tx fault, transmitter enable, interrupt, and topstat logic tx fault logic the tx fault logic provides detection of transmitter faults with fault indication bits located in the txstat1 and txstat2 registers. any of the individual faults can be masked using the fmsk1 and fmsk2 registers. any fault indication bit, if masked, will flag but will not create a fault condition. when a fault condition occurs and is not masked, the transmitter will shut down unless masked by fmsk_txflt. to restart the transmitter after a shutdown has occurred, the source of the fault must be removed and either the disable pin is toggled or the modectrl register has 68h written to it. the fault logic is shown in figure 18. figure 16. rssi circuitry figure 17. loopback block diagram figure 15. external temperature sense circuit rssi 5 100 pf adc 1.62v rssi current from tia max 3956 rout rin touta tin rx _ pol tx _ pol rx _ lb _ en [ 1 : 0 ] 00 11 tx _ lb _ en [ 1 : 0 ] 00 11 tin los tx _ sq _ mode [ 1 : 0 ] rin los sq _ en toutc max 3956 parasitic resistance mmbt3906lt1 100pf tsns tgnd i temp (12.5a to 200a) MAX3956 maxim integrated 37 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
transmitter enable logic the requirements for the transmitter to be enabled are shown in figure 19. startup complete is a delay that allows the on-chip systems to become stable after power- up and is typically 100s. interrupt programmable logic intrpt is a programmable pin that provides a trigger for real-time monitoring of internal status bits. status regis - ters rxstat, txstat1, txstat2, txstat3, txstat4, and ddmstat23 contain the bits that generate interrupt signals. each of the bits in these registers can be indi - vidually masked if desired. if masked, the bit will still flag upon detection of its flag condition but the flag will not propagate to the intrpt pin or the topstat register. additional interrupts are por and if unflagged, tx fault. the interrupt logic is shown in figure 20. topstat logic status registers rxstat, txstat1, txstat2, txstat3, txstat4, and ddmstat23 feed the topstat regis - ter along with signals tx fault, p3v sense, and por. topstat bits pord and p3vflag will be set to 1 after power-up or a por event. these bits are sticky therefore need to be read to be cleared. the topstat logic diagram is shown in figure 21. figure 18. fault logic figure 19. transmitter enable logic txstat1 pg.1; h0x21 [7] [5] [3] [2] [1] tin_los lvflag lv_touta lv_toutc lv_vout m m m m m [7] [5] [3] [2] [1] fmsk1 pg.0; h0x5c m m [3] [1] fmsk2 pg.0 h0x5d txstat2; pg.1; h0x22 mod_ovfl mdin_open [7] [4] [0] mdin_shrt m [0] fault pin fault latch por, disable, modectrl = 68h rst por m [5] fmsk2 pg.0; h0x5d from interrupt logic (masked by default) to interrupt logic (masked by default) to transmitter enable logic to topstat [0] indicates a mask bit that, when set to a logic 1, will mask the stat bit from flagging the downstream logic m startup complete fault ( from tx fault logic ) tx _ en disable ( pin ) dis _ pol xcvr _ en lvflag m transmitter enable m fmsk 2 pg . 0 ; h 0 x 5 d [ 6 ] [ 0 ] fmsk 1 pg . 0 ; h 0 x 5 c tx output touta toutc vout maxim integrated 38 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
figure 20. interrupt logic m m m m m m rxstat; pg.1; h0x1d [1] [0] rxlos_copy rxlosref [4] [3] intmsk1 pg.0 h0x5e txstat1; pg.1; h0x21 [7] [5] [3] [2] [1] tin_los lvflag lv_touta lv_toutc lv_vout [7] [5] [3] [2] [1] intmsk2 pg.0 h0x5f txstat2; pg.1; h0x22 [7] [5] [4] [3] [6] [0] dc_ovfl mdin_open dc_udfl mod_ovfl mod_udfl mdin_shrt m m m m [7] [6] [5] [4] intmsk3 pg.0 h0x60 m m [7] [4] intmsk4 pg.0 h0x61 txstat3; pg.1; h0x23 [5] [4] [3] [6] [0] ssmodeb md0_ovfl md0_udfl md1_ovfl md1_udfl m m [3] [2] m [1] m m [7] [6] intmsk5 pg.0 h0x62 txstat4; pg.1; h0x24 [3] [4] set_apc_ovfl set_apc_udfl m m [5] [4] ddmstat23; pg.1; h0x54 [7] [4] [3] [6] [0] ddm_tmin ddm_tmax ddm_p2vflag ddm_rssi_hi_fail ddm_rssi_lo_fail ddm_ext_t_fail ddm_lvflag [2] [1] [5] [3] [6] [0] [2] [1] m [4] intmsk6; pg.0 h0x63 from tx fault logic (masked by default) to tx fault logic (masked by default) m intmsk2 pg.0; h0x5f [0] por intrpt pin m indicates a mask bit that, when set to a logic 1, will mask the stat bit from flagging the downstream logic [ 5] m m m m m m m maxim integrated 39 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
figure 21. topstat logic m m m m m m m pord * [ 7 ] pord _ inv * [ 6 ] p 3 vflag * [ 5 ] rx _ int [ 4 ] tx _ int [ 3 ] apc _ int [ 2 ] ddm _ int [ 1 ] tx _ fault _ copy [ 0 ] rxlosref * [ 1 ] [ 0 ] rxlos _ copy * txstat 1 ; pg . 1 ; h 0 x 21 [ 7 ] [ 5 ] [ 3 ] [ 2 ] [ 1 ] tin _ los * lvflag * lv _ touta * lv _ toutc * lv _ vout * m m m m m m txstat 2 ; pg . 1 ; h 0 x 22 [ 7 ] [ 5 ] [ 4 ] [ 3 ] [ 6 ] [ 0 ] dc _ ovfl * mdin _ open * dc _ udfl * mod _ ovfl * mod _ udfl * mdin _ shrt * m m m txstat 3 ; pg . 1 ; h 0 x 23 [ 5 ] [ 4 ] [ 3 ] [ 6 ] [ 0 ] ssmodeb * md 0 _ ovfl * md 0 _ udfl * md 1 _ ovfl * md 1 _ udfl * m m m m m m m m m txstat 4 ; pg . 1 ; h 0 x 24 [ 3 ] [ 4 ] set _ apc _ ovfl * set _ apc _ udfl * m m ddmstat 23 ; pg . 1 ; h 0 x 54 [ 7 ] [ 4 ] [ 3 ] [ 6 ] [ 0 ] ddm _ tmin * ddm _ tmax * ddm _ p 2 vflag * ddm _ rssi _ hi _ fail * ddm _ rssi _ lo _ fail * ddm _ ext _ t _ fail * ddm _ lvflag * [ 2 ] [ 1 ] tx fault topstat pg . 1 ; h 0 x 1 c * these bits are sticky and , once flagged , remain flagged ( logic 1 ) until they are read m indicates a mask bit that , when set to a logic 1 , will mask the stat bit from flagging the downstream logic p 3 v sense por sense rxstat ; pg . 1 ; h 0 x 1 d maxim integrated 40 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
the following are two different ways for using topstat: using the intrpt pin ? mask any undesired flags ? when intrpt asserts, read topstat to narrow down the flag source. the flagged topstat bit indi - cates the type of interrupt flagged (apc, ddm, etc) and which stat register(s) must be read to locate the source of the flag, see figure 21. ? read the register(s) that triggered the topstat bit that is flagged. the individual source of the flag will remain flagged in the stat register until it is read. not using the intrpt pin ? mask any undesired flags ? periodically read topstat to determine if any inter - rupts have flagged. ? if a topstat bit has flagged, read the register(s) responsible for triggering that topstat bit to deter - mine the specific source of the flag. table 11. registers and addresses for page 0 page address name default value function x h0x00 modectrl 00h mode control register 0 h0x3f ddmctrl1 64h upper byte of external temp sensor scale factor 0 h0x40 ddmctrl2 24h lower byte of external temp sensor scale factor 0 h0x41 ddmctrl3 88h upper byte of external temp sensor offset factor 0 h0x42 ddmctrl4 93h lower byte of external temp sensor offset factor 0 h0x43 ddmctrl5 64h upper byte of internal temp sensor scale factor 0 h0x44 ddmctrl6 f3h lower byte of internal temp sensor scale factor 0 h0x45 ddmctrl7 88h upper byte of internal temp sensor offset factor 0 h0x46 ddmctrl8 93h lower byte of internal temp sensor offset factor 0 h0x47 ddmctrl9 80h ddm averaging, dc monitor control register 0 h0x49 calreg1 xxh calibration constant register. do not overwrite. see the load factory calibration constants section in the design procedure for the required calibration constants loading procedure. 0 h0x4a calreg2 xxh 0 h0x4b calreg3 xxh 0 h0x4c calreg4 xxh 0 h0x4d calreg5 xxh 0 h0x4e rxctrl1 61h receiver control register 0 h0x4f rxctrl2 e8h receiver control register 0 h0x50 rxctrl3 4bh receiver control register 0 h0x51 rxctrl4 c4h receiver control register 0 h0x52 rxctrl5 0bh receiver control register 0 h0x53 rxctrl6 a0h receiver control register 0 h0x55 set_cml 09h receiver output voltage dac 0 h0x56 set_los 10h receiver loss-of-signal threshold setting 0 h0x58 los_masktime 00h los output masking time setting 0 h0x59 txctrl1 0fh transmitter control register 0 h0x5a txctrl2 12h transmitter control register maxim integrated 41 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
table 11. registers and addresses for page 0 (continued) register descriptions MAX3956 mode control register (modectrl), address: h0x00 (page independent) ddm control register (ddmctrl1), address: h0x3f (page 0) page address name default value function 0 h0x5c fmsk1 70h transmitter fault mask register 0 h0x5d fmsk2 3fh transmitter fault mask register 0 h0x5e intmsk1 7fh transmitter interrupt mask register 0 h0x5f intmsk2 ffh transmitter interrupt mask register 0 h0x60 intmsk3 ffh transmitter interrupt mask register 0 h0x61 intmsk4 ffh transmitter interrupt mask register 0 h0x62 intmsk5 f0h transmitter interrupt mask register 0 h0x63 intmsk6 7fh transmitter interrupt mask register 0 h0x67 topctrl1 00h tx to rx loopback control register 0 h0x68 topctrl2 00h rx to tx loopback control register bit d[7:0] description bit name modectrl [7:0] 00h = normal mode C read-only mode with exception of all increment registers (default) 12h = setup mode C enables write permission clears after each write operation 68h = fault clear mode C clears all faults including the fault latch at fault pin there are two register address page select settings: 55h = select page-1 (default) 81h = select page-0 read-back returns 0 when page 0 is selected and 1 when page 1 is selected read/write r/w por state 00h normal mode & page 0 reset upon read no bit d[7:0] description bit name tsns_ext_scl[15:8] this is the upper byte of the external temperature sense scale factor. this byte, along with the lower byte represents a 16-bit, unsigned value. read/write r/w write in setup mode only por state 64h maxim integrated 42 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
ddm control register (ddmctrl2), address: h0x40 (page 0) ddm control register (ddmctrl3), address: h0x41 (page 0) ddm control register (ddmctrl4), address: h0x42 (page 0) ddm control register (ddmctrl5), address: h0x43 (page 0) ddm control register (ddmctrl6), address: h0x44 (page 0) bit d[7:0] description bit name tsns_ext_scl[7:0] this is the lower byte of the external temperature sense scale factor. this byte, along with the upper byte represents a 16-bit, unsigned value. read/write r/w write in setup mode only por state 24h bit d[7:0] description bit name tsns_ext_ofs[15:8] this is the upper byte of the external temperature offset term. this, along with the lower byte represents a 16-bit, unsigned value. tsns_ext_ofs[15:0] is divided by 128 then subtracted from the scaled external-temperature data, see figure 14. read/write r/w write in setup mode only por state 88h bit d[7:0] description bit name tsns_ext_ofs[7:0] this is the lower byte of the external temperature offset term. this, along with the upper byte represents a 16-bit, unsigned value. tsns_ext_ofs[15:0] is divided by 128 then subtracted from the scaled external-temperature data, see figure 14. read/write r/w write in setup mode only por state 93h bit d[7:0] description bit name tsns_int_scl[15:8] this is the upper byte of the internal temperature scale factor. this, along with the lower byte represents a 16-bit, unsigned value. read/write r/w write in setup mode only por state 64h bit d[7:0] description bit name tsns_int_scl[7:0] this is the lower byte of the internal temperature scale factor. this, along with the upper byte represents a 16-bit, unsigned value. read/write r/w write in setup mode only por state f3h maxim integrated 43 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
ddm control register (ddmctrl7), address: h0x45 (page 0) ddm control register (ddmctrl9), address: h0x47 (page 0) calibration register (calreg1), address: h0x49 (page 0) bit d[7:0] description bit name tsns_int_ofs[15:8] this is the upper byte of the internal temperature offset term. this, along with the lower byte represents a 16-bit, unsigned value. tsns_int_ofs[15:0] is divided by 128 then subtracted from the scaled internal-temperature data, see figure 14. read/write r/w write in setup mode only por state 88h ddm control register (ddmctrl8), address: h0x46 (page 0) bit d[7:0] description bit name tsns_int_ofs[7:0] this is the lower byte of the internal temperature offset term. this, along with the upper byte represents a 16-bit, unsigned value. tsns_int_ofs[15:0] is divided by 128 then subtracted from the scaled internal-temperature data, see figure 14. read/write r/w write in setup mode only por state 93h bit d7 d[6:3] d2 d[1:0] bit name ddm_avg res ddm_txrpt_sel res read/write r/w, write in setup mode only por state 1 0000 0 00 bit name description d[7] ddm_avg enables ddm averaging. 0 = no averaging 1 = 4x averaging (default) d[6:3] res reserved d[2] ddm_txrpt_sel controls what the ddm_txrpt register reports 0 = tx dc current monitor (default) 1 = tx average current monitor d[1:0] res reserved bit d7 d6 d5 d4 d3 d2 d1 d0 bit name res cal1[6] cal1[5] cal1[4] cal1[3] cal1[2] cal1[1] cal1[0] read/write r r/w, write in setup mode only por state 0 x x x x x x x factory-calibrated register. do not overwrite. calibration constants must be loaded after por. see load factory calibration constants. maxim integrated 44 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
calibration register (calreg2), address: h0x4a (page 0) calibration register (calreg3), address: h0x4b (page 0) calibration register (calreg5), address: h0x4d (page 0) calibration register (calreg4), address: h0x4c (page 0) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name res cal2[6] cal2[5] cal2[4] cal2[3] cal2[2] cal2[1] cal2[0] read/write r r/w, write in setup mode only por state 0 x x x x x x x factory calibrated register. do not overwrite. calibration constants must be loaded after por. see load factory calibration constants. bit d[7:6] d5 d4 d3 d2 d1 d0 bit name res cal3[5] cal3[4] cal3[3] cal3[2] cal3[1] cal3[0] read/write r r/w write in setup mode only por state 00 x x x x x x factory-calibrated register. do not overwrite. calibration constants must be loaded after por. see load factory calibration constants. bit d[7:4] d3 d2 d1 d0 bit name res cal4[3] cal4[2] cal4[1] cal4[0] read/write r r/w, write in setup mode only por state 0000 x x x x factory-calibrated register. do not overwrite. calibration constants must be loaded after por. see load factory calibration constants. bit d7 d6 d5 d4 d3 d2 d1 d0 bit name cal5[7] cal5[6] cal5[5] cal5[4] cal5[3] cal5[2] cal5[1] cal5[0] read/write r/w, write in setup mode only por state x x x x x x x x factory-calibrated register. do not overwrite. calibration constants must be loaded after por. see load factory calibration constants. maxim integrated 45 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
receiver control register (rxctrl1), address: h0x4e (page 0) bit d7 d6 d5 d4 d[3:1] d0 bit name res rx_en rx_out_en sq_en res rx_pol read/write r r/w, write in setup mode only por state 0 1 1 0 000 1 bit name description d[7] res reserved d[6] rx_en enables rx core circuitry 0 = disabled C powers down the entire rx section 1 = enabled (default) d[5] rx_out_en this bit directly controls the mode of the rx output stage 0 = disabled to common-mode voltage 1 = enabled (default) d[4] sq_en this bit enables control of the rx output stage by means of los event 0 = disabled (default) 1 = enabled los event disables the rx output stage to common mode d[3:1] res reserved. must be set to 000 for proper operation. d[0] rx_pol sets polarity of the rx receiver path 0 = inverted 1 = normal (default) maxim integrated 46 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
receiver control register (rxctrl3), address: h0x50 (page 0) receiver control register (rxctrl2), address: h0x4f (page 0) bit d7 d6 d5 d[4:3] d[2:0] bit name res rsel_pol rate_sel set_rxbw[1:0] set_rxde[2:0] read/write r/w, write in setup mode only por state 1 1 1 01 000 bit name description d[7] res reserved. must be set to 1 for proper operation. d[6] rsel_pol sets polarity of the rsel pin 0 = inverted 1 = normal (default) d[5] rate_sel rate select bit. logical or combination of this bit and rsel pin controls rx path selection. 0 = low-bandwidth mode 1 = high-bandwidth mode (default) d[4:3] set_rxbw[1:0] set_rxbw sets the -3db bw of the lowpass flter in a low bw rx path the meaning of the two bits changes with rx data path selection. see below: rate_sel + rsel = 0 rate_sel + rsel = 1 00 = 1ghz 01 = high-bandwidth mode (default) 01 = 2ghz all others = reserved 10 = 2.5ghz 11 = 3ghz d[2:0] set_rxde[2:0] sets deemphasis for the rx output stage to compensate for fr4 loss at 10gbps 0xx = disabled (default) 100 = 1db deemphasis 101 = 2db deemphasis 110 = 3db deemphasis 111 = 4db deemphasis bit d[7:3] d[2:1] d0 bit name res az_bw[1:0] res read/write r/w, write in setup mode only por state 01001 01 1 bit name description d[7:3] res reserved d[2:1] az_bw[1:0] selects the auto-zero bandwidth 00 = 5khz 01 = 10khz (default) 10 = 20khz 11 = 40khz d[0] res reserved maxim integrated 47 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
receiver control register (rxctrl5), address: h0x52 (page 0) receiver control register (rxctrl6), address: h0x53 (page 0) bit d7 d6 d[5:0] bit name res los_pol res read/write r/w, write in setup mode only por state 1 1 000100 bit name description d[7] res reserved d[6] los_pol selects the los polarity 0 = inverted 1 = normal (default) d[5:0] res reserved bit d[7:4] d3 d[2:0] bit name res los_en res read/write r/w, write in setup mode only por state 0000 1 011 bit name description d[7:4] res reserved d[3] los_en los enable 0 = disabled 1 = enabled (default) d[2:0] res reserved bit d[7:5] d4 d[3:0] bit name res los_pu_en res read/write r/w, write in setup mode only por state 101 0 0000 bit name description d[7:5] res reserved d[4] los_pu_en enables active pullup on los pin. when enabled the los output becomes a push-pull cmos output. 0 = disabled, open-drain output (default) 1 = enabled, push-pull cmos output d[3:0] res reserved receiver control register (rxctrl4), address: h0x51 (page 0) maxim integrated 48 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
receiver control register (set_cml), address: h0x55 (page 0) receiver control register (rxctrl7), address: h0x56 (page 0) bit d[7:5] d4 d3 d2 d1 d0 bit name res set_cml[4] set_cml[3] set_cml[2] set_cml[1] set_cml[0] read/write r/w, write in setup mode only por state 000 0 1 0 0 1 bit name description d[7:5] res reserved d[4:0] set_cml[4:0] set rx output amplitude. amplitudes listed below are valid for set_rxde = 0xx 0 0000 = 400mv p-p 0 1001 = 600mv p-p (default) 1 1111 = 1v p-p bit d7 d6 d5 d4 d3 d2 d1 d0 bit name set_los [6] set_los [5] set_los [4] set_los [3] set_los [2] set_los [1] set_los [0] res read/write r/w, write in setup mode only por state 0 0 0 1 0 0 0 0 bit name description d[7:1] set_ los[6:0] set los threshold. assert threshold approximately 1.2mv p-p set_los[6:0]. deassert threshold is approximately 1.6 the assert threshold to avoid los chatter due to noise. 00 0000 = minimum assert level 00 1000 = 9.6mv p-p differential (default) 11 1111 = maximum assert level d[0] res reserved maxim integrated 49 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
transmitter control register (txctrl1), address: h0x59 (page 0) receiver control register (los_masktime), address: h0x58 (page 0) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name res los_mask time[6] los_mask time[5] los_ mask time[4] los_mask time[3] los_mask time[2] los_mask time[1] los_mask time[0] read/write r/w, write in setup mode only por state 0 0 0 0 0 0 0 0 bit name description d[7] res reserved d[6:0] los_masktime[6:0] sets masking time for los. the lsb size is 36s. 000 0000 = 0s (default) bit d7 d[6:5] d4 d3 d[2:1] d0 bit name low_dc_en res fault_pu_en fault_pol res tx_pol read/write r/w, write in setup mode only por state 0 00 0 1 11 1 bit name description d[7] low_dc_en enables low-dc current mode when low laser threshold current is needed 0 = disabled (default) 1 = enabled d[6:5] res reserved d[4] fault_pu_en enables active pull-up on fault pin. when enabled the fault output becomes a push-pull cmos output. 0 = disabled, open-drain output (default) 1 = enabled, push-pull cmos output d[3] fault_pol sets fault pin polarity 0 = inverted 1 = normal (default) d[2:1] res reserved d[0] tx_pol sets tx data path polarity 0 = inverted 1 = normal (default) maxim integrated 50 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
transmitter control register (txctrl2), address: h0x5a (page 0) bit d[7:5] d4 d3 d2 d1 d0 bit name res dis_pol tx_eq[1] tx_eq[0] tx_sq_mode[1] tx_sq_mode[0] read/write r/w write in setup mode only por state 000 1 0 0 1 0 bit name description d[7:5] res reserved d[4] dis_pol sets polarity of disable pin 0 = inverse 1 = normal (default) d[3:2] tx_eq[1:0] selects tx input equalization 00 = 1.5db boost at 5.1ghz (default) 01 = 3db boost at 5.1ghz 10 = 4.5db boost at 5.1ghz 11 = 5.5db boost at 5.1ghz d[1:0] tx_sq_mode[1:0] tx output squelch-modes during tin los event 00 = no current into toutc pin 01 = sink current set to a midlevel corresponding to p avg at current temperature 10 = modulation current is disabled but apc loop remains active (default) 11 = squelch disabled maxim integrated 51 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
fault mask control register (fmsk1), address: h0x5c (page 0) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name fmsk_ lvflag res fmsk_ tin_los res fmsk_ touta fmsk_ toutc fmsk_ vout fmsk_ txflt read/write r/w write in setup mode only por state 0 1 1 1 0 0 0 0 the fmsk1 register sets mask bits preventing individual events to latch fault at fault pin. bit name description d[7] fmsk_lvflag mask lvflag fault condition on v ccto pin 0 = no mask (default) 1 = mask d[6] res reserved d[5] fmsk_tin_los mask tin_los fault condition 0 = unmasked 1 = mask (default) d[4] res reserved d[3] fmsk_touta mask lv_touta fault condition 0 = no mask (default) 1 = mask d[2] fmsk_toutc mask lv_toutc fault condition 0 = no mask (default) 1 = mask d[1] fmsk_vout mask lv_vout fault condition 0 = no mask (default) 1 = mask d[0] fmsk_txflt masks the fault latch signal, which controls the output stage on/off behavior. 0 = no mask (default) 1 = mask when fmsk1[0] = 1, output stage behavior becomes independent of fault conditions. maxim integrated 52 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
fault mask control register (fmsk2), address: h0x5d (page 0) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name fmsk_ lvflag_ outdis fmsk_ intrpt_ fault res fmsk_ mdin_open res fmsk_ mod_ovfl fmsk_ mdin_shrt read/write r/w write in setup mode only por state 0 0 1 1 1 1 1 1 the fmsk2 register sets mask bits preventing individual events to latch fault at fault pin. bit name description d[6] fmsk_lvflag_outdis mask tx output disable during lvflag event 0 = no mask (default) 1 = mask d[5] fmsk_intrpt_fault mask logic or combination of interrupt event and fault event at f ault pin. 0 = no mask 1 = mask (default) d[4] res reserved d[3] fmsk_mdin_open mask mdin_open fault condition 0 = no mask 1 = mask (default) d[2] res reserved d[1] fmsk_mod_ovfl mask mod_ovfl fault condition. threshold set by modmax register. 0 = no mask 1 = mask (default) d[0] fmsk_mdin_shrt mask mdin_shrt fault condition 0 = no mask 1 = mask (default) maxim integrated 53 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
interrupt mask control register (intmsk2), address: h0x5f (page 0) interrupt mask control register (intmsk1), address: h0x5e (page 0) bit d[7:5] d4 d3 d[2:0] bit name res intmsk_rxlosref intmsk_rxlos res read/write r/w write in setup mode only por state 011 1 1 111 the intmsk1 register sets mask bits preventing individual events to latch interrupt at intrpt pin. bit name description d[7:5] res reserved d[4] intmsk_rxlosref mask rxlosref interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[3] intmsk_rxlos mask rxlos copy from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[2:0] res reserved bit d7 d6 d5 d4 d3 d2 d1 d0 bit name intmsk_ lvflag res intmsk_ tin_los res intmsk_ touta intmsk_ toutc intmsk_ vout intmsk_ fault read/write r/w write in setup mode only por state 1 1 1 1 1 1 1 1 the intmsk2 register sets mask bits preventing individual events to latch interrupt at intrpt pin. bit name description d[7] intmsk_lvflag mask lvflag interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[6] res reserved d[5] intmsk_tin_los mask tin_los interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[4] res reserved d[3] intmsk_touta mask lv_touta interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[2] intmsk_toutc mask lv_toutc interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[1] intmsk_vout mask lv_vout interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[0] intmsk_fault mask fault event from intrpt pin 0 = no mask 1 = mask (default) maxim integrated 54 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
interrupt mask control register (intmsk3), address: h0x60 (page 0) bit d7 d6 d5 d4 d[3:0] bit name intmsk_dc_ovfl intmsk_dc_udfl intmsk_mod_ovfl intmsk_mod_udfl res read/write r/w write in setup mode only por state 1 1 1 1 1111 the intmsk3 register sets mask bits preventing individual events to latch interrupt at intrpt pin. bit name description d[7] intmsk_dc_ovfl mask dc_ovfl interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[6] intmsk_dc_udfl mask dc_udfl interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[5] intmsk_mod_ovfl mask mod_ovfl interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[4] intmsk_mod_udfl mask mod_udfl interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[3:0] res reserved maxim integrated 55 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
interrupt mask control register (intmsk4), address: h0x61 (page 0) bit d7 d[6:5] d4 d3 d2 d1 d0 bit name intmsk_ mdopen res intmsk_ mdin_shrt intmsk_ ssmode intmsk_ md0ovfl intmsk_ md0udfl res read/write r/w write in setup mode only por state 1 11 1 1 1 1 1 the intmsk4 register sets mask bits preventing individual events to latch interrupt at intrpt pin. bit name description d[7] intmsk_mdopen mask mdin_open interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[6:5] res reserved d[4] intmsk_mdin_shrt mask mdin_shrt interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[3] intmsk_ssmode mask ssmode interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[2] intmsk_md0ovfl mask md0_ovfl interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[1] intmsk_md0udfl mask md0_udfl interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[0] res reserved maxim integrated 56 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
interrupt mask control register (intmsk5), address: h0x62 (page 0) bit d7 d6 d5 d4 d[3:0] bit name intmsk_md1ovfl intmsk_md1udfl intmsk_ setapc_ovfl intmsk_ setapc_udfl res read/write r/w write in setup mode only por state 1 1 1 1 0000 the intmsk5 register sets mask bits preventing individual events to latch interrupt at intrpt pin. bit name description d[7] intmsk_md1ovfl mask md1_ovfl interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[6] intmsk_md1udfl mask md1_udfl interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[5] intmsk_setapc_ovfl mask set_apc_ovfl interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[4] intmsk_setapc_udfl mask set_apc_udfl interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[3:0] res reserved maxim integrated 57 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
interrupt mask control register (intmsk6), address: h0x63 (page 0) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name res intmsk_ ddmtmax intmsk_ ddmtmin intmsk_ddm_ lvflag intmsk_ p2vflag intmsk_ rssi_hi intmsk_ rssi_lo intmsk_ ext_tf read/write r/w write in setup mode only por state 0 1 1 1 1 1 1 1 the intmsk6 register sets mask bits preventing individual events to latch interrupt at intrpt pin. bit name description d[7] res reserved d[6] intmsk_ddmtmax mask ddm_tmax interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[5] intmsk_ ddmtmin mask ddm_tmin interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[4] intmsk_ddm_ lvflag mask ddm_lvflag interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[3] intmsk_ p2vflag mask ddm_p2vflag interrupt (vccx and vcct) from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[2] intmsk_rssi_hi mask ddm rssi reading stuck high interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[1] intmsk_rssi_lo mask ddm rssi reading stuck low interrupt from intrpt pin and topstat register 0 = no mask 1 = mask (default) d[0] intmsk_ext_tf mask ddm_ext_t_fail external temperature reading fag/fault interrupt (missing connection to external pnp) from intrpt pin and topstat register 0 = no mask 1 = mask (default) maxim integrated 58 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
tx to rx loopback control register (topctrl1), address: h0x67 (page 0) rx to tx loopback control register (topctrl2), address: h0x68 (page 0) table 12. registers and addresses for page 1 bit d[7:6] d[5:4] d[3:0] bit name res tx_lb_en[1:0] res read/write r/w write in setup mode only por state 00 00 0000 the topctrl1 register enables signal loopback from the tx input to the rx output. bit name description d[7:6] res reserved d[5:4] tx_lb_ en[1:0] transmitter loopback enable 00 = tx to rx loopback disabled (default) 01 = reserved 11 = tx to rx loopback enabled 10 = reserved d[3:0] res reserved bit d[7:6] d[5:4] d[3:0] bit name res rx_lb_en[1:0] res read/write r/w write in setup mode only por state 00 00 0000 the topctrl2 register enables signal loopback from the rx input to the tx output. bit name description d[7:6] res reserved d[5:4] rx_lb_en[1:0] receiver loopback enable 00 = rx to tx loopback disabled (default) 01 = reserved 11 = rx to tx loopback enabled 10 = reserved d[3:0] res reserved page address name default value function x h0x00 modectrl 00h mode control register 1 h0x01 txctrl3 02h transmitter control register 1 h0x02 txctrl4 0ah transmitter control register 1 h0x0a txctrl5 08h transmitter control register 1 h0x0b txctrl6 80h transmitter control register 1 h0x0c dcmax 12h this register sets the [9:2] set_dc dac code limit 1 h0x0d modmax 30h this register sets the [8:1]set_mod dac code limit 1 h0x0e set_dc 00h laser dc current dac initial value 1 h0x0f set_mod 00h laser modulation current dac initial value maxim integrated 59 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
table 12. registers and addresses for page 1 (continued) page address name default value function 1 h0x10 dcinc 00h set_dc dac twos complement increment register 1 h0x11 modinc 00h set_mod dac twos complement increment register 1 h0x12 set_apc 80h apc loop target setting register 1 h0x13 apcinc 00h set_apc target twos complement increment register 1 h0x14 txctrl7 14h transmitter control register 1 h0x15 topctrl3 90h transceiver control register 1 h0x16 dcreg 00h laser dc current dac read-back 1 h0x17 modreg 00h laser modulation current dac read-back 1 h0x18 md1regh 00h upper byte of digitized top peak value of md input current 1 h0x19 md1regl 00h lower byte of digitized top peak value of md input current 1 h0x1a md0regh 00h upper byte of digitized bottom peak value of md input current 1 h0x1b md0regl 00h lower byte of digitized bottom peak value of md input current 1 h0x1c topstat a0h transceiver status register 1 h0x1d rxstat 10h receiver status register 1 h0x21 txstat1 00h transmitter status register 1 h0x22 txstat2 00h transmitter status register 1 h0x23 txstat3 00h transmitter status register 1 h0x24 txstat4 00h transmitter status register 1 h0x3e ddmstat1 00h upper byte of digitized rssi value 1 h0x3f ddmstat2 00h lower byte of digitized rssi value 1 h0x40 ddmstat3 00h upper byte of digitized vccx value 1 h0x41 ddmstat4 00h lower byte of digitized vccx value 1 h0x42 ddmstat5 00h upper byte of digitized vcct value 1 h0x43 ddmstat6 00h lower byte of digitized vcct value 1 h0x44 ddmstat7 00h upper byte of digitized vccto value 1 h0x45 ddmstat8 00h lower byte of digitized vccto value 1 h0x46 ddmstat9 00h upper byte of digitized auxiliary voltage value at badc pin 1 h0x47 ddmstat10 00h lower byte of digitized auxiliary voltage value at badc pin 1 h0x48 ddmstat11 00h upper byte of digitized external temp-sensor value at tsns pin 1 h0x49 ddmstat12 00h lower byte of digitized external temp-sensor value at tsns pin 1 h0x4a ddmstat13 00h upper byte of digitized internal temp-sensor value 1 h0x4b ddmstat14 00h lower byte of digitized internal temp-sensor value 1 h0x4c ddmstat15 00h ddm status register & upper 4 bits of dc monitor current value 1 h0x4d ddmstat16 00h lower byte of dc monitor current value 1 h0x4e ddmstat17 00h upper byte of digitized tx power value 1 h0x4f ddmstat18 00h lower byte of digitized tx power value 1 h0x54 ddmstat23 00h ddm status register maxim integrated 60 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
transmitter control register (txctrl3), address: h0x01 (page 1) transmitter control register (txctrl4), address: h0x02 (page 1) bit d7 d[6:2] d1 d0 bit name loop_stop res autorng_en soft_reset read/write r/w write in setup mode only por state 0 0 0000 1 0 bit name description d[7] loop_stop halts the apc loop. this bit can only be changed from a 1 to a 0 by writing 1 to loop_run. 0 = no action (default) 1 = halts apc loop d[6:2] res reserved d[1] autorng_en enables auto-ranging of mdin_gain. 0 = auto-ranging disabled 1 = auto-ranging enabled. when using apcinc the MAX3956 will automatically adjust gain setting of mdin_gain in order to keep set_apc in the range of 127 to 255 (default) d[0] soft_reset soft reset will reset all registers to their default (por) values. the tx must be disabled, via disable pin or tx_en bit, before a soft reset can occur. 0 = no action (default) 1 = soft reset bit d[7:2] d1 d0 bit name res mdavg_cnt res read/write r/w write in setup mode only por state 00 0010 1 0 bit name description d[7:2] res reserved d[1] mdavg_cnt select averaging depth for the mdin signal. 0 = 32 averaging 1 = 256 averaging (default) d[0] res reserved maxim integrated 61 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
transmitter control register (txctrl5), address: h0x0a (page 1) transmitter control register (txctrl6), address: h0x0b (page 1) bit d7 d6 d5 d4 d[3:0] bit name res apc_en ibupdt_en imupdt_en res read/write r/w write in setup mode only por state 0 0 0 0 1000 bit name description d[7] res reserved d[6] apc_en enables apc loop 0 = disabled (default) 1 = enabled d[5] ibupdt_en sets the way dcreg[9:0] is written to: apc enabled: 0 = maintains last value of dcreg[9:0] in initialization (default) 1 = fault/por/restart initializes dcreg[9:2] with set_dc[7:0] apc off: 0 = dcreg can only be changed by writing to dcinc[4:0] (default) 1 = if ibupdt_en is already set to 1 a write to set_dc[7:0] is passed to dcreg[9:2] d[4] imupdt_en sets the way modreg[9:0] is written to: 0 = modreg can only be changed by writing to modinc[4:0] (default) 1 = if imupdt_en is already set to 1 a write to set_mod[7:0] is passed to modreg[8:1] d[3:0] res reserved bit d[7:1] d0 bit name res aux_restart read/write r/w write in setup mode only por state 1 0 bit name description d[7:1] res reserved d[0] aux_restart enables restarting of apc loop by means of disable pin. 0 = disabled (default) 1 = enabled maxim integrated 62 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
maximum dc-current register (dcmax), address: h0x0c (page 1) maximum modulation-current register (modmax), address: h0x0d (page 1) initial or open-loop dc current register (set_dc), address: h0x0e (page 1) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name dcmax [7] dcmax [6] dcmax [5] dcmax [4] dcmax [3] dcmax [2] dcmax [1] dcmax [0] read/write r/w write in setup mode only por state 0 0 0 1 0 0 1 0 the dcmax register limits the maximum digital code setting in dcreg current dac control register . bit name description d[7:0] dcmax[7:0] programs the maximum settable dc current (limits the maximum value that can be written to the dcreg[9:2] register). note that it only relates to the eight most signifcant bits of the dcreg register. i dcmax = (dcmax[7:0] + 3) x 234a 18d = 4.9ma dc current limit (default) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name modmax [7] modmax [6] modmax [5] modmax [4] modmax [3] modmax [2] modmax [1] modmax [0] read/write r/w write in setup mode only por state 0 0 1 1 0 0 0 0 the modmax register limits the maximum digital code setting in modreg current dac control register . bit name description d[7:0] modmax[7:0] programs the maximum settable modulation current (limits the maximum value that can be written to the modreg[8:1] register). note that it only relates to the eight msbs of the modreg register . i modmax = (modmax[7:0] + 8) x 468a 48d = 26ma p-p modulation current limit (default) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name set_dc [7] set_dc [6] set_dc [5] set_dc [4] set_dc [3] set_dc [2] set_dc [1] set_dc [0] read/write r/w write in setup mode only por state 0 0 0 0 0 0 0 0 the set_dc register set the initial or open-loop laser dc current. bit name description d[7:0] set_dc[7:0] programs the initial or open-loop dc current. the value in this register is sent to the dcreg[9:0] registers eight msbs . i dc = (set_dc[7:0] + 3) x 234a 0d = 0.7ma dc current (default) maxim integrated 63 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
modulation current register (set_mod), address: h0x0f (page 1) dc current increment register (dcinc), address: h0x10 (page 1) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name set_mod [7] set_mod [6] set_mod [5] set_mod [4] set_mod [3] set_mod [2] set_mod [1] set_mod [0] read/write r/w write in setup mode only por state 0 0 0 0 0 0 0 0 the set_mod register sets modulation current. bit name description d[7:0] set_mod[7:0] programs the modulation current. the value in this register is sent to the modreg[8:0] registers eight msbs . i mod = (set_mod[7:0] + 8) x 468a 0d = 3.7ma p-p modulation current (default) bit d[7:5] d4 d3 d2 d1 d0 bit name res dcinc[4] dcinc[3] dcinc[2] dcinc[1] dcinc[0] read/write r r/w write in any mode por state 000 0 0 0 0 0 the dcinc register increments/decrements code in dcreg dac control register as described below . bit name description d[7:5] res reserved d[4:0] dcinc[4:0] mode when apc enabled: dcinc[3:0] controls the maximum allowed step and hence infuences apc loop dynamics especially during startup. x 0000 = 0 maximum step allowed for dcreg[9:0] x 1111 = 15d maximum step allowed for dcreg[9:0] mode when apc disabled: laser dc current increment/decrement applied to dcreg[9:0] upon write (two s complement number, the range is +15/-16). 1 0000 = subtract 16 from dcreg[9:0] 0 1111 = add 15 to dcreg[9:0] maxim integrated 64 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
modulation increment register (modinc), address: h0x11 (page 1) average md current target register (set_apc), address: h0x12 (page 1) apc increment register (apcinc), address: h0x13 (page 1) bit d[7:5] d4 d3 d2 d1 d0 bit name res modinc[4] modinc[3] modinc[2] modinc[1] modinc[0] read/write r r/w write in any mode por state 000 0 0 0 0 0 the modinc register increments/decrements code in modreg dac control register as described below . bit name description d[7:5] res reserved d[4:0] modinc[4:0] laser modulation current increment/decrement applied to modreg[8:0] upon write (two s complement number, the range is +15/-16). 1 0000 = subtract 16 from modreg[8:0] 0 1111 = add 15 to modreg[8:0] bit d7 d6 d5 d4 d3 d2 d1 d0 bit name set_ apc[7] set_ apc[6] set_ apc[5] set_ apc[4] set_ apc[3] set_ apc[2] set_ apc[1] set_ apc[0] read/write r/w write in setup mode only por state 1 0 0 0 0 0 0 0 the set_apc register sets the average laser power for the apc loop (see the design procedure section for more information). bit name description d[7:0] set_apc [7:0] sets the closed-loop mdin target average current. this closed-loop current depends on set_ apc and mdin_gain registers. bit d[7:4] d3 d2 d1 d0 bit name res apcinc[3] apcinc[2] apcinc[1] apcinc[0] read/write r r/w write in any mode por state 0000 0 0 0 0 the apcinc register increments/decrements the set_apc register. bit name description d[7:4] res reserved d[3:0] apcinc[3:0] increments or decrements the set_apc[7:0] value with the twos complement value from apcinc[3:0] (the range is +7/-8). 1000 = subtract 8 from set_apc[7:0] 0111 = add 7 to set_apc[7:0] maxim integrated 65 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
transmitter control register (txctrl7), address: h0x14 (page 1) transceiver control register (topctrl3), address: h0x15 (page 1) bit d[7:3] d2 d1 d0 bit name res mdin_gain[2] mdin_gain[1] mdin_gain[0] read/write r/w write in setup mode only por state 0 0010 1 0 0 bit name description d[7:3] res reserved d[2:0] mdin_gain[2:0] selects the transimpedance gain of the mdin input 000 = 156 011 = 1248 001 = 312 1xx = 2496 (default) 010 = 624 bit d7 d6 d[5:3] d2 d1 d0 bit name loop_run loop_restart res loop_th tx_en xcvr_en read/write r/w write in setup mode only por state 1 0 010 0 0 0 bit name description d[7] loop_run controls the apc loop. loop_run can only be changed from a 1 to a 0 by writing a 1 to loop_stop. 0 = no action 1 = apc loop will restart from last saved prefreeze conditions (subject to ibupdt_en) d[6] loop_ restart forces apc loop out of steady-state and enables the start-up state machine 0 = no action (default) 1 = restart d[5:3] res reserved d[2] loop_th sets threshold for updating dcreg 0 = 0.125 lsb (default) 1 = 0.75 lsb d[1] tx_en enables the tx data path, control loop, and the dc current and modulation current dacs. 0 = tx disabled (default) 1 = tx enabled d[0] xcvr_en top-level transceiver enable 0 = disabled (default) 1 = enabled maxim integrated 66 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
dc current dac readback register (dcreg), address: h0x16 (page 1) modulation current dac readback register (modreg), address: h0x17 (page 1) monitor diode top peak (averaged) register (md1regh), address: h0x18 (page 1) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name dcreg [9] dcreg [8] dcreg [7] dcreg [6] dcreg [5] dcreg [4] dcreg [3] dcreg [2] read/write read only por state 0 0 0 0 0 0 0 0 reset upon read no no no no no no no no the dcreg register provides a read-back value of the dc current dac. bit name description d[7:0] dcreg[9:2] dc current dac readback. the two lsbs for this register are located at page 1 address: h0x24[2:1]. bit d7 d6 d5 d4 d3 d2 d1 d0 bit name modreg [8] modreg [7] modreg [6] modreg [5] modreg [4] modreg [3] modreg [2] modreg [1] read/write read only por state 0 0 0 0 0 0 0 0 the modreg register provides a read-back value of the mod current dac. bit name description d[7:0] modreg[8:1] modulation current dac readback. the lsb for this register is located at page 1 address: h0x24[0]. bit d7 d6 d5 d4 d3 d2 d1 d0 bit name md1reg [15] md1reg [14] md1reg [13] md1reg [12] md1reg [11] md1reg [10] md1reg [9] md1reg [8] read/write read only por state 0 0 0 0 0 0 0 0 reset upon read no no no no no no no no the md1regh register provides a read-back value of the digitized top peak current at md input. bit name description d[7:0] md1reg[15:8] stored (averaged) value for monitor-diode current peak corresponding to optical p1. md1regh is the upper 8 bits of the 16-bit value md1reg[15:0]. maxim integrated 67 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
monitor diode top peak (averaged) register (md1regl), address: h0x19 (page 1) monitor diode bottom peak (averaged) register (md0regl), address: h0x1b (page 1) monitor diode bottom peak (averaged) register (md0regh), address: h0x1a (page 1) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name md1reg [7] md1reg [6] md1reg [5] md1reg [4] md1reg [3] md1reg [2] md1reg [1] md1reg [0] read/write read only por state 0 0 0 0 0 0 0 0 reset upon read no no no no no no no no the md1regl register provides a read-back value of the digitized top peak current at md input. bit name description d[7:0] md1reg[7:0] stored (averaged) value for monitor-diode current peak corresponding to optical p1. md1regl is the lower 8 bits of the 16-bit value md1reg[15:0]. bit d7 d6 d5 d4 d3 d2 d1 d0 bit name md0reg [15] md0reg [14] md0reg [13] md0reg [12] md0reg [11] md0reg [10] md0reg [9] md0reg [8] read/write read only por state 0 0 0 0 0 0 0 0 reset upon read no no no no no no no no the md0regh register provides a read-back value of the digitized bottom peak current at md input. bit name description d[7:0] md0reg[15:8] stored (averaged) value for monitor-diode current peak corresponding to optical p0. md0regh is the upper 8 bits of the 16-bit value md0reg[15:0]. bit d7 d6 d5 d4 d3 d2 d1 d0 bit name md0reg [7] md0reg [6] md0reg [5] md0reg [4] md0reg [3] md0reg [2] md0reg [1] md0reg [0] read/write read only por state 0 0 0 0 0 0 0 0 reset upon read no no no no no no no no the md0regl register provides a read-back value of the digitized bottom peak current at md input. bit name description d[7:0] md0reg[7:0] stored (averaged) value for monitor-diode current peak corresponding to optical p0. md0regl is the lower 8 bits of the 16-bit value md0reg[15:0]. maxim integrated 68 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
top level status register (topstat), address: h0x1c (page 1) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name pord pord_inv p3vflag rx_int tx_int apc_int ddm_int tx_fault_ copy read/write read only por state 1 0 1 0 0 0 0 0 reset upon read yes* yes* yes* no no no no no *sticky bitonce fagged these registers remain fagged (logic 1) until they are read. once read, they are reset to 0 if the source of the fag has been removed. the topstat register is a status register for the top-level circuitry. bit name description d[7] pord power-on-reset of the digital core. v dd vs. 1.3v 0 = deasserted 1 = asserted (default) d[6] pord_inv inverse of pord 0 = deasserted (default) 1 = asserted d[5] p3vflag v ccx /v cct vs. 2.5v 0 = deasserted 1 = asserted (default) d[4] rx_int interrupt/fault in rx group. read rxstat. 0 = deasserted (default) 1 = asserted d[3] tx_int interrupt/fault in tx group. read txstat1 and txstat2. 0 = deasserted (default) 1 = asserted d[2] apc_int interrupt/fault in apc group. read txstat2, txstat3, and txstat4 0 = deasserted (default) 1 = asserted d[1] ddm_int interrupt/fault in ddm group. read ddmstat23. 0 = deasserted (default) 1 = asserted d[0] tx_fault_copy a copy of fault pin value 0 = deasserted (default) 1 = asserted maxim integrated 69 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
receiver status register (rxstat), address: h0x1d (page 1) bit d[7:5] d4 d[3:2] d1 d0 bit name res rx_rate res rxlosref rxlos_copy read/write read only por state 000 1 00 0 0 reset upon read n/a no n/a yes* yes* *sticky bit- once fagged these registers remain fagged (logic 1) until they are read. once read, they are reset to 0 if the source of the fag has been removed. bit name description d[7:5] res reserved d[4] rx_rate receiver data-rate setting. it is the logical or of the rsel pin and rate_sel bit. 0 = rx set for < 4g operation 1 = rx set for > 4g operation d[3:2] res reserved d[1] rxlosref interrupt rx los block reference signal failure 0 = deasserted (default) 1 = asserted d[0] rxlos_copy a copy of rx los pin value 0 = deasserted (default) 1 = asserted maxim integrated 70 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
transmitter status register (txstat1), address: h0x21 (page 1) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name lvflag res tin_los res lv_touta lv_toutc lv_vout tx_dis_ copy read/write read only por state 0 0 0 0 0 0 0 0 reset upon read yes* no yes* yes* yes* yes* yes* no *sticky bit- once fagged these registers remain fagged (logic 1) until they are read. once read, they are reset to 0 if the source of the fag has been removed. bit name description d[7] lvflag interrupt/fault: v cct or v ccto under-voltage detection 0 = deasserted (default) 1 = asserted d[6] res reserved d[5] tin_los interrupt/fault: indicates tin ac signal too low 0 = deasserted (default) 1 = asserted d[4] res reserved d[3] lv_touta interrupt/fault: touta open or shorted to gnd. 0 = deasserted (default) 1 = asserted d[2] lv_toutc interrupt/fault: toutc open or shorted to gnd. 0 = deasserted (default) 1 = asserted d[1] lv_vout interrupt/fault: vout fault under-voltage detection (referenced to v ccto ) 0 = deasserted (default) 1 = asserted d[0] tx_dis_copy copy of disable pin. polarity, controlled by dis_pol, is included in this bit. maxim integrated 71 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
transmitter status register (txstat2), address: h0x22 (page 1) bit d7 d6 d5 d4 d3 d[2:1] d0 bit name mdin_ open dc_ ovfl dc_ udfl mod_ ovfl mod_ udfl res mdin_shrt read/write read only por state 0 0 0 0 0 00 0 reset upon read yes* yes* yes* yes* yes* no yes* *sticky bitonce fagged these registers remain fagged (logic 1) until they are read. once read, they are reset to 0 if the source of the fag has been removed. bit name description d[7] mdin_open interrupt/fault: mdin pin open 0 = deasserted (default) 1 = asserted d[6] dc_ovfl interrupt: dcreg input over maximum warning 0 = deasserted (default) 1 = asserted d[5] dc_udfl interrupt: dcreg input underfow warning 0 = deasserted (default) 1 = asserted d[4] mod_ovfl interrupt/fault: modreg input over maximum warning 0 = deasserted (default) 1 = asserted d[3] mod_udfl interrupt: modreg input underfow warning 0 = deasserted (default) 1 = asserted d[2:1] res reserved d[0] mdin_shrt interrupt/fault: mdin shorted to ground or supply. 0 = deasserted (default) 1 = asserted maxim integrated 72 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
transmitter status register (txstat3), address: h0x23 (page 1) bit d7 d6 d5 d4 d3 d2 d[1:0] bit name ssmode ssmodeb md0_ovfl md0_udfl md1_ovfl md1_udfl res read/write read only por state 0 1 0 0 0 0 00 reset upon read no yes* yes* yes* yes* yes* no *sticky bitonce fagged these registers remain fagged (logic 1) until they are read. once read, they are reset to 0 if the source of the fag has been removed. bit name description d[7] ssmode apc steady-state mode monitor 0 = acquisition mode (default) 1 = steady-state mode d[6] ssmodeb apc inverted steady-state mode monitor 0 = steady-state mode 1 = acquisition mode (default) d[5] md0_ovfl interrupt: md0reg input over maximum warning 0 = deasserted (default) 1 = asserted d[4] md0_udfl interrupt: md0reg input underfow warning 0 = deasserted (default) 1 = asserted d[3] md1_ovfl interrupt: md1reg input over maximum warning 0 = deasserted (default) 1 = asserted d[2] md1_udfl interrupt: md1reg input underfow warning 0 = deasserted (default) 1 = asserted d[1:0] res reserved maxim integrated 73 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
ddm status register (ddmstat1), address: h0x3e (page 1) ddm status register (ddmstat2), address: h0x3f (page 1) transmitter status register (txstat4), address: h0x24 (page 1) bit d[7:5] d4 d3 d2 d1 d0 bit name res set_apc_ ovfl set_apc_ udfl dcreg[1] dcreg[0] modreg[0] read/write read only por state 000 0 0 0 0 0 reset upon read no yes* yes* no no no *sticky bitonce fagged these registers remain fagged (logic 1) until they are read. once read, they are reset to 0 if the source of the fag has been removed. bit name description d[7:5] res reserved d[4] set_apc_ovfl interrupt: apcinc setting attempting to overfow set_apc register 0 = deasserted (default) 1 = asserted d[3] set_apc_udfl (autorng_en=1) interrupt: set_apc below minimum value. 0 = deasserted (default) 1 = asserted (autorng_en = 0) interrupt: set_apc below 64d. 0 = deasserted (default) 1 = asserted d[2:1] dcreg[1:0] lsbs of dcreg register d[0] modreg[0] lsb of modreg register bit d[7:0] description bit name ddm_rssi [15:8] reports upper byte of the measured value of rssi. read/write read only por state 00h bit d[7:0] description bit name ddm_rssi [7:0] reports lower byte of the measured value of rssi. read/write read only por state 00h maxim integrated 74 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
ddm status register (ddmstat4), address: h0x41 (page 1) ddm status register (ddmstat6), address: h0x43 (page 1) ddm status register (ddmstat8), address: h0x45 (page 1) ddm status register (ddmstat5), address: h0x42 (page 1) ddm status register (ddmstat7), address: h0x44 (page 1) ddm status register (ddmstat3), address: h0x40 (page 1) bit d[3:0] description bit name ddm_vccx [11:8] reports upper nibble of the measured value of vccx. the ddm_vccx[11:0] value is unsigned with full scale of 4.658v. see the electrical characteristics for vccx operational range. read/write read only por state 00h bit d[7:0] description bit name ddm_vccx [7:0] reports lower byte of the measured value of vccx. the ddm_vccx[11:0] value is unsigned with full scale of 4.658v. see the electrical characteristics for vccx operational range. read/write read only por state 00h bit d[3:0] description bit name ddm_vcct [11:8] reports upper nibble of the measured value of vcct. the ddm_vcct[11:0] value is unsigned with full scale of 4.658v. see the electrical characteristics for vcct operational range. read/write read only por state 00h bit d[7:0] description bit name ddm_vcct [7:0] reports lower byte of the measured value of vcct. the ddm_vcct[11:0] value is unsigned with full scale of 4.658v. see the electrical characteristics for vcct operational range. read/write read only por state 00h bit d[3:0] description bit name ddm_vccto [11:8] reports upper nibble of the measured value of vccto. the ddm_vccto[11:0] value is unsigned with full scale of 4.658v. see the electrical characteristics for vccto operational range. read/write read only por state hx00 bit d[7:0] description bit name ddm_vccto [7:0] reports lower byte of the measured value of vccto. the ddm_vccto[11:0] value is unsigned with full scale of 4.658v. see the electrical characteristics for vccto operational range. read/write read only por state 00h maxim integrated 75 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
ddm status register (ddmstat10), address: h0x47 (page 1) ddm status register (ddmstat12), address: h0x49 (page 1) ddm status register (ddmstat14), address: h0x4b (page 1) ddm status register (ddmstat11), address: h0x48 (page 1) ddm status register (ddmstat13), address: h0x4a (page 1) ddm status register (ddmstat9), address: h0x46 (page 1) bit d[3:0] description bit name ddm_badc [11:8] reports upper nibble of the measured voltage value badc pin. the ddm_badc[11:0] value is unsigned with full scale of 1.164v. read/write read only por state 00h bit d[7:0] description bit name ddm_badc [7:0] reports lower byte of the measured voltage value badc pin. the ddm_badc[11:0] value is unsigned with full scale of 1.164v. read/write read only por state 00h bit d[7:0] description bit name ddm_ext_tsns [15:8] reports upper byte of the measured value of external temperature sensor between the pins tsns and tgnd. this is the signed integer portion of the external temperature result (range: -128c to +127c). read/write read only por state 00h bit d[7:0] description bit name ddm_ext_tsns [7:0] reports lower byte of the measured voltage value of external temperature sensor between the pins tsns and tgnd. this is the fractional portion of the external temperature result (range: 0c to 255/256c). read/write read only por state 00h bit d[7:0] description bit name ddm_int_tsns [15:8] reports upper byte of the measured value of internal temperature sensor . this is the signed integer portion of the internal temperature result (range: -128c to +127c). read/write read only por state 00h bit d[7:0] description bit name ddm_int_tsns [7:0] reports lower byte of the measured voltage value of internal temperature sensor . this is the fractional portion of the internal temperature result (range: 0c to 255/256c). read/write read only por state 00h maxim integrated 76 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
ddm status register (ddmstat16), address: h0x4d (page 1) ddm status register (ddmstat17), address: h0x4e (page 1) ddm status register (ddmstat15), address: h0x4c (page 1) ddm status register (ddmstat18), address: h0x4f (page 1) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name res ddm_ tx_shdn res ddm_ tin_los ddm_ txrpt[11] ddm_ txrpt[10] ddm_ txrpt[9] ddm_ txrpt[8] read/write read only por state 0 0 0 0 0 0 0 0 reset upon read no no no no no no no no the ddmstat15 register is a status register showing fags with impact on digital monitors. bit name description d[7] res reserved d[6] ddm_tx_shdn tx status fag 0 = normal operation (default) 1 = shut down (due to por, fault, disable, tx_en=0, or xcvr_en = 0) d[5] res reserved d[4] ddm_tin_los loss-of-signal at tin 0 = deasserted (default) 1 = asserted d[3:0] ddm_txrpt[11:8] reports the measured value of dc or average laser current. this is the upper nibble of txb. these bits along with the lower byte in ddmstat16 make up the 12-bit value. bit d[7:0] description bit name ddm_txrpt [7:0] reports lower byte of dc or average laser current. the ddm_txrpt_sel bit in ddm_ctrl9 register selects whether dc or average laser current is reported. read/write read only por state 00h bit d[3:0] description bit name ddm_txp [11:8] reports the measured value of the monitor diode current which represents average laser power. this is the upper nibble of the 12-bit value. read/write read only por state 00h bit d[7:0] description bit name ddm_txp [7:0] reports the measured value of the monitor diode current which represents average laser power. this is the lower byte of the 12-bit value. read/write read only por state 00h maxim integrated 77 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
ddm status register (ddmstat23), address: h0x54 (page 1) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name ddm_ tmax ddm_ tmin res ddm_ p2vflag ddm_rssi_ hi_fail ddm_rssi_ lo_fail ddm_ext_ t_fail ddm_ lvflag read/write read only por state 0 0 0 0 0 0 0 0 reset upon read yes* yes* no yes* yes* yes* yes* yes* *sticky bitonce fagged these registers remain fagged (logic 1) until they are read. once read, they are reset to 0 if the source of the fag has been removed. bit name description d[7] ddm_tmax interrupt: internal temperature above +120c. 0 = deasserted (default) 1 = asserted d[6] ddm_tmin interrupt: internal temperature below -50c. 0 = deasserted (default) 1 = asserted d[5] res reserved d[4] ddm_p2vflag interrupt: vccx/vcct vs. 2.1v 0 = deasserted (default) 1 = asserted d[3] ddm_rssi_hi_fail interrupt: rssi is stuck high. 0 = deasserted (default) 1 = asserted d[2] ddm_rssi_lo_fail interrupt: rssi is stuck low. 0 = deasserted (default) 1 = asserted d[1] ddm_ext_t_fail interrupt: status indicating that the external temperature sense has failed. when this condition occurs, the external temperature is forced to -128c. 0 = deasserted (default) 1 = asserted d[0] ddm_lvflag interrupt: supply voltage too low for accurate ddm measurement. 0 = deasserted (default) 1 = asserted maxim integrated 78 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
layout considerations the high-speed data inputs and outputs are the most criti - cal paths for the device, and great care should be taken to minimize discontinuities on these transmission lines between the connector and the ic. the following are some suggestions for maximizing the devices performance: ? the data inputs should be wired directly between the connector and ic without stubs. ? the data transmission lines to the laser should be kept as short as possible, and the impedance of the transmission lines must be considered part of the laser matching network. ? an uninterrupted ground plane should be positioned beneath the high-speed i/os. ? ground path vias should be placed close to the ic and the input/output interfaces to allow a return cur - rent path to the ic and the laser. ? maintain 100 differential transmission line imped - ance for the rin, rout, and tin i/os. ? the data transmission lines to the laser should be kept as short as possible, and must be designed for 50 differential or 25 single-ended characteristic impedance. ? use good high-frequency layout techniques and mul - tilayer boards with an uninterrupted ground plane to minimize emi and crosstalk. refer to the schematic and board layers of the hfrd-67 reference design data sheet for more information. exposed-pad package and thermal consider - ations the exposed pad on the MAX3956 is the only electrical connection to ground and provides a very low-thermal resistance path for heat removal from the ic. the pad is also electrical ground on the device and must be sol - dered to the circuit board ground for proper thermal and electrical performance. refer to application note 862: hfan-08.1: thermal considerations of qfn and other exposed-paddle packages for additional information. maxim integrated 79 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
10g rosa pin rin+ rin- rssi v ccx v ccro 4 .7k to 10k v cchost los v ccto touta toutc vout mdin tsns tgnd mmbt3906lt1 csel sda scl intrpt 3.3v rout+ rout- fr4 microstrip z diff = 100 regfilt tin+ tin- z 0 = 25 z 0 = 25 fr4 microstrip z diff = 100 0.01f 0.01f 0.01f 0.01f fault disable tx_fault disable c c8051f393 scl sda sfp+ 10gbase-lr module 20-pin connector host board 10gbps dfb tosa MAX3956 asic 4 .7k to 10k v cchost rso rsel 0 .01f v cct los 0.01f 20 20 0.1f 10pf blm15ax102 0.1f 0.01f 19nh 19nh 100pf 5 0.1f v dd 10 10pf 100 pf 0.1pf 0.1pf blm15ax102 typical application circuit maxim integrated 80 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
part temp range pin-package MAX3956etj+ -40c to +85c 32 tqfn-ep* package type package code outline no. land pattern no. 32 tqfn-ep t3255+3 21-0140 90-0001 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos ordering information note: parts are guaranteed by design and characterization to operate over the -40c to +95c ambient temperature range (t a ) and are tested up to +95c. +denotes a lead(pb)-free/rohs-compliant package. *exposed pad. maxim integrated 81 MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface www.maximintegrated.com
revision number revision date description pages changed 0 8/13 initial release 1 2/14 fixed errors in electrical characteristics , detailed description , figure 7, figure 8, figure 14, table 11, ddm control register tables, design procedure , fault mask control register, ddm status register tables, and typical application circuit 7, 22, 26, 27, 35, 41, 43, 44, 50, 53, 75, 76, 80 2 6/14 fixed errors in electrical characteristics , power-on-reset (por) section, figure 18, and the MAX3956 mode control register, ddm control register, fault mask control register, transmitter status register tables, and typical application circuit 6, 27, 38, 42, 44, 53, 72, 80 3 9/14 updated the electrical characteristics and added toc27 to typical operating characteristics 2, 11 revision history ? 2014 maxim integrated products, inc. 82 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. MAX3956 11.3gbps transceiver with ddm and dc-coupled laser interface for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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